Dimitris Metafas

A fast DCT processor, based on special purpose CORDIC rotators

In this paper, a new processor that computes the Discrete Cosine Transform (DCT) is presented. Based on a recently proposed DCT algorithm, this architecture overcomes the major drawbacks of the original implementation resulting in a design with considerably less area consumption and higher speed. To achieve these results, a novel architecture, based on the CORDIC circular rotation algorithm, is introduced: it reduces the required area by more than 60% compared to the use of standard CORDIC architectures. Furthermore, bit serial arithmetic is used, resulting in a very compact design. In order to get maximum throughput, the proposed processor is fully pipelined, achieving a performance efficient even for signals as fast as HDTV.<<ETX>>

A floating point pipeline CORDIC processor with extended operation set

A novel architecture of a digital signal processing (DSP) floating point, pipelined processor is presented which is based on the CORDIC and CCM algorithms. It provides for the first time a single hardware structure with a full set of elementary arithmetic operations which include circular and hyperbolic functions, square root, logarithm as well as multiplication and division. Its powerful functionality makes it an ideal processing element in high speed multiprocessor applications, e.g. real-time DSP and matrix equation solving problems.<<ETX>>

A DSP processor with a powerful set of elementary arithmetic operations based on cordic and CCM algorithms

Abstract A novel architecture of a DSP processor is presented here, which is derived from the combination of the CORDIC and CCM algorithms. It performs a full set of elementary arithmetic operations which are circular and hyperbolic functions, square root, logarithm as well as multiplication and division. The architecture is fully parallel and pipelined resulting in a very high throughput.

Implementation of Given's rotation processors for DSP real-time applications

Abstract In this paper, a special purpose, fully parallel and pipelined, CORDIC processor that performs Givens Rotations is presented. The Givens Rotation (GR) processor is based on modifications of the original CORDIC circular rotation algorithm, so that the decoupling between the word length of the input/output signals and the resolution of the angle, to be accomplished. Exploiting this feature and also using the CORDIC representation of the rotation angle a significant reduction of the chip area is achieved. A methodology for the determination of the architectural parameters according to the application requirements is presented, as well as the VLSI implementation of a specific GR processor for high fidelity audio applications. The implemented processor performs 4 × 10 7 vector rotations per second. In the last part of this paper, the design of a high throughput digital equalizer based on the GR processor is presented which processes simultaneously 1,000 independent filters.

A floating-point advanced cordic processor

In this paper, a novel architecture of a floating-point digital signal processor is presented. It introduces a single hardware structure with a full set of elementary arithmetic functions which includessin, cos, tan, arctanh, circular rotation andvectoring, sinh, cosh, tanh, arctanh, hyperbolic rotation andvectoring, square root, logarithm, exponential as well asaddition, multiplication anddivision. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) and the Convergence Computing Method (CCM) algorithms for computing arithmetic functions and it is fully parallel and pipelined. Its advanced functionality is achieved without significant increase in hardware, in comparison to ordinary CORDIC processor, and makes it an ideal processing element in high speed multiprocessor applications, e.g. real time Digital Signal Processing (DSP) and computer graphics.

Real-time communication protocol development using SDL for an embedded system on chip based on ARM microcontroller

The rising complexity of communication protocols forces designers to work with efficient high level software design tools to increase the level of abstraction at which they work. For the purposes of the software development of a DECT/GSM protocol implementation for an embedded system a novel SDL based framework was followed. The embedded real time system on chip is based on a multiprocessor architecture, featuring an ARM and a DSP core. Complete systems architecture is presented along with the architecture of the software parts. Final protocol stack code was automatically generated from the SDL tool. A new advanced RTOS-SDL integration method was utilised to integrate the generated code with the functions and services of the RTOS. The results of this integration method were quite promising and the produced system met the initial specifications within the development time limits.

Architecture and VLSI module generator for expressing digital signals in decibels

Abstract An architecture and automatic parametric VLSI design for expressing digital signals in decibels is presented. Both the piece-wise linear approximation and a look-up table ROM was used to compute the logarithm involved. The round-off error analysis is also given and the optimal wordlength of the various sections of the hardware for all input/output requirements is described. A module generator implementing the simplified architecture is presented, it is independent of technology and design rules, accepts any standard cell library, has a wide range of parameters, is easy to use and can be readily interfaced to other CAD tools.

A Multi-level Validation Methodology for Wireless Network Applications *

This paper presents the validation methodology established and ap-plied during the development of a wireless LAN application. The target of the development is the implementation of the hardware physical layer of the HIPERLAN/2 wireless LAN protocol and its interface with the upper layers. The implementation of the physical layer (modem) has been validated in two different levels. First, at the functional level, the modem was validated by a high-level UML model. Then, at the implementation level, a new validation framework drives the validation procedure at three different sub-levels of de-sign abstraction (numerical representation, VHDL coding, FPGA-based proto-typing). Using this validation methodology, the prototype of the HIPERLAN/2 modem has been designed and validated successfully.

A UML-based methodology for the system design of a wireless LAN prototype

This paper proposes a new methodology for the system design and development of wireless network protocols. The proposed methodology used UML and its real-time extensions at its basis. This system design methodology formalizes the system specification and validation phases. Furthermore, wireless system design is enhanced by the concept of high-level system codesign, which can be achieved by the use of UML in the system design. The presented methodology has been applied to the design of the industrial prototype implementation of a wireless network node based on the HIPERLAN/2 standard. The system design of the HIPERLAN/2 prototype is presented in details, with special information given on the system architecture and the implementation of the hardware and software parts of the system. The application of the presented system methodology helped in the reduction of the development time and effort for the HIPERLAN/2 prototype

CORDIC based pipeline architecture for all-pass filters7

An efficient pipeline architecture for normalized lattice all-pass filters is introduced. This is a fully parametric architecture which realizes concurrently /spl lambda/ different mth order all-pass digital filters using a number of m n-stage pipelined coordinate rotations digital computer (CORDIC) processors. The architecture is based on a special purpose CORDIC processing element which performs Givens rotations. A large number of filters is obtained exploiting the pipeline architecture and making use of the pipeline interleaving technique. The design procedure of an efficient digital equalizer based on the proposed normalized all-pass filter architecture is presented.<<ETX>>