Christos Drosos

Real-time communication protocol development using SDL for an embedded system on chip based on ARM microcontroller

The rising complexity of communication protocols forces designers to work with efficient high level software design tools to increase the level of abstraction at which they work. For the purposes of the software development of a DECT/GSM protocol implementation for an embedded system a novel SDL based framework was followed. The embedded real time system on chip is based on a multiprocessor architecture, featuring an ARM and a DSP core. Complete systems architecture is presented along with the architecture of the software parts. Final protocol stack code was automatically generated from the SDL tool. A new advanced RTOS-SDL integration method was utilised to integrate the generated code with the functions and services of the RTOS. The results of this integration method were quite promising and the produced system met the initial specifications within the development time limits.

A Multi-level Validation Methodology for Wireless Network Applications *

This paper presents the validation methodology established and ap-plied during the development of a wireless LAN application. The target of the development is the implementation of the hardware physical layer of the HIPERLAN/2 wireless LAN protocol and its interface with the upper layers. The implementation of the physical layer (modem) has been validated in two different levels. First, at the functional level, the modem was validated by a high-level UML model. Then, at the implementation level, a new validation framework drives the validation procedure at three different sub-levels of de-sign abstraction (numerical representation, VHDL coding, FPGA-based proto-typing). Using this validation methodology, the prototype of the HIPERLAN/2 modem has been designed and validated successfully.

A UML-based methodology for the system design of a wireless LAN prototype

This paper proposes a new methodology for the system design and development of wireless network protocols. The proposed methodology used UML and its real-time extensions at its basis. This system design methodology formalizes the system specification and validation phases. Furthermore, wireless system design is enhanced by the concept of high-level system codesign, which can be achieved by the use of UML in the system design. The presented methodology has been applied to the design of the industrial prototype implementation of a wireless network node based on the HIPERLAN/2 standard. The system design of the HIPERLAN/2 prototype is presented in details, with special information given on the system architecture and the implementation of the hardware and software parts of the system. The application of the presented system methodology helped in the reduction of the development time and effort for the HIPERLAN/2 prototype

On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal

For the implementation of a multi-mode DECT/GSM wireless terminal, a dual mode baseband processor, namely ASPIS processor, capable to undertake all baseband signal processing required is designed and fabricated. The multi-mode wireless terminal is based on direct conversion architecture. Experimental results from the operation of ASPIS processor and performance analysis of the selected architecture, under two different testing environments, are promising and quite satisfactory.

The low power analogue and digital baseband processing parts of a novel multimode DECT/GSM/DCS1800 terminal

In order to support a multimode DECT/GSM/DCS1800 terminal architecture, with low power characteristics and integrated support for direct conversion terminal architecture, the critical parts of such a terminal were designed and implemented using three different chips. These parts include a baseband processor, a modem and suitable analogue parts. The baseband processor was designed to support multimode operation, all baseband processing required and different terminal architectures (heterodyne or direct conversion). The modem features a GMSK/GFSK modulator and a novel, low power detection algorithm supports a direct conversion terminal. The analogue circuitry includes analogue filters and Digital-to-Analog and Analog-to-Digital converters. The architecture of the direct conversion wireless terminal is presented along with details on the low power characteristics of the processor and the modem. Experimental results from the operation of the multimode terminal are presented.

A HIPERLAN/2 - IEEE 802.11a Reconfigurable System-on-Chip

In this paper the design of a partly reconfigurable System-on-Chip (SoC) for wireless LANs is described. The reconfigurable System-on-Chip will realize both HIPERLAN/2 and IEEE 802.11a wireless LAN systems. The initial version of the system will include Mobile Terminal functionality. Future firmware versions will upgrade systems functionality to allow its operation as Access Point. Functionality for operation in outdoor environments in wireless point-to-point links will be also targeted by future firmware upgrades. A systems prototype is currently under development on the ARM integrator platform.

The low power baseband processing parts of a novel dual mode DECT/GSM terminal

In order to support a dual mode DECT/GSM terminal architecture, with low power characteristics and integrated support for direct conversion terminal architecture the basic parts of such a terminal were designed and implemented. These parts include a baseband processor and a modem. The baseband processor is designed to support dual mode operation, all baseband processing required and different terminal architectures (heterodyne or direct conversion). The modem features a GMSK/GFSK modulator and a novel, low power detection algorithm that supports direct conversion terminals. The architecture of the direct conversion wireless terminal is presented along with details on the low power characteristics of the processor and the modem. Experimental results from the operation of the terminal are also presented.