Christian Schippel

Gate-Recessed AlGaN/GaN Based Enhancement-Mode High Electron Mobility Transistors for High Frequency Operation

By combining a low damage chlorine based gate-recess etching and a sophisticated technology for AlGaN/GaN depletion-mode high electron mobility transistors (HEMTs) we fabricated high performance recessed enhancement-mode HEMTs. A comparative investigation of depletion- and enhancement-mode devices prepared by this technique shows excellent DC and RF properties. A transconductance of 540 mS/mm and cut-off frequencies fT of 39 GHz and fmax of 74 GHz were obtained for 0.25 µm gate enhancement-mode HEMTs. Large-signal power measurements at 2 GHz reveal an output power density of 4.6 W/mm at 68% PAE conclusively demonstrating the capability of our enhancement-mode devices.

Quantum Effects on the Gate Capacitance of Trigate SOI MOSFETs

Scaling effects on the gate capacitance of trigate MOS field-effect transistors are studied by means of analytical models and numerical self-consistent solutions of the 2-D Schrödinger and Poisson equations. Special attention is paid to the quantum capacitance, which is related to the density of states. We show that, although the quantum capacitance strongly decreases when the channel dimensions are scaled, the gate capacitance is not reduced relative to the oxide capacitance in trigate MOS structures. This is due to the fact that both the oxide capacitance and the quantum capacitance scale with the channel cross section. From Schrödinger-Poisson simulations, we actually observe a relative increase in the gate capacitance when the silicon cross section is scaled below 7 nm × 7 nm, whereas the opposite trend is obtained from classical calculations. We relate this mainly to the differences between quantum-mechanical and classical electron distributions in real space. Quantization effects on the quantum capacitance are found to have less effect on the gate capacitance except for very small silicon cross sections in the order of 2 nm × 2 nm.

Empirical Model for the Effective Electron Mobility in Silicon Nanowires

An empirical model for the effective electron mobility in silicon nanowires (SiNWs) is presented. The model is based on published mobility data from numerical simulations of electron transport in SiNWs with different cross sections. Both phonon scattering and surface roughness scattering as well as the impact of the effective vertical field are considered. A comparison with a variety of experimental mobility data from the literature shows that the model can be treated as a reference for benchmarking different NW technologies. The effective field dependence is modeled by a simple expression making our mobility model very efficient for the use in numerical device simulators or in analytical MOSFET models.

Performance Trends of Si-Based RF Transistors

This paper discusses several aspects of the performance of advanced Si-based RF transistors. The RF performance of SiGe HBTs and Si RF MOSFETs is reviewed and compared to that of III-V RF transistors. The speed - breakdown voltage tradeoff which is typical for bipolar transistors is discussed with special emphasis on SiGe HBTs. On the field-effect transistor side, we review the performance of state-of-the-art Si RF MOSFETs and show that these devices are highly competitive in terms of speed and cutoff frequency.

RF performance of 28nm PolySiON and HKMG CMOS devices

The impact of scaling in advanced RF/MS-CMOS has been extensively discussed but there has not been a publication that compares the RF characteristics of 28nm high-K metal gate HKMG and PolySiON technologies fabricated in the same facility. In this work, we show that HKMG improves transistor fT and increases varactor tunning range. However, it can actually decrease fmax. We examine how process features made to optimize cost and digital performance impact the RF performance. Process features which improve DC current and gm, including HKMG also give higher fT. However, fmax is sensitive to gate resistance and PolySiON has an advantage here.

Low-power, wide supply voltage bandgap reference circuit in 28nm CMOS

This paper presents an integrated bandgap reference circuit which is addressing low current consumption and a wide supply voltage range, using a current mode structure. Embedded in a sophisticated Power Management Unit (PMU) for a GNSS receiver, this bandgap reference has an output of 0.60 V and it can reach a temperature coefficient of 33 ppm/°C in the range from -40 °C to 125 °C. With a 1.4 V supply voltage, the power is only 3.5 μW and the PSRR is 57 dB at DC frequency. Occupying 0.125 mm2 chip area, this bandgap reference has been implemented in the CMOS 28 nm technology from Globalfoundries and successfully validated in the lab.

The influence of collector designs on fmax versus ft characteristics for different types of Si-based RF bipolar transistors

The cut-off frequency ft, the maximum frequency of oscillation fmax and the collector–emitter breakdown voltage BVCEO are computed for various types of Si-based bipolar transistors with different selectively implanted collector (SIC) profiles. In particular, the influence of SIC profiles on ft versus BVCEO and fmax versus BVCEO characteristics is investigated. Subsequently, the fmax versus ft behaviour is discussed. It is shown that for slow transistors (BJTs) there is a trade-off between ft and fmax. However, in the case of faster HBTs this trend can be reversed.

High-voltage low-power startup backup battery switch using low voltage devices in 28nm CMOS

This paper presents a 4.8 V tolerant circuit for reliably switching a startup load between a main power supply and a battery power supply. The circuit automatically switches the main power supply over to the battery in case the main line has been interrupted. The circuit includes a pair of back-to-back switch transistors for isolating the load from each power supply, a bias circuit for controlling the switch transistors, two independent current sources and two current subtraction units for deciding which supply to provide to the load. It consumes less than 1 µA per input and it can supply a startup circuitry up to 50 µA. The circuit has been implemented in a CMOS 28 nm technology, using only “low-voltage” devices and was successfully validated in the lab.