Christian Zuniga

Flare in extreme ultraviolet lithography: metrology, out-of-band radiation, fractal point-spread function, and flare map calibration

The critical role of flare in extreme ultraviolet (EUV) lithography is well known. In this work, the implementation of a robust flare metrology is discussed, and the proposed approach is qualified both in terms of precision and accuracy. The flare measurements are compared to full-chip simulations using a simplified single fractal point-spread function (PSF), and the parameters of the analytical PSF are optimized by comparing the simulation output to the experimental results. After flare map calibration, the matching of simulation and experiment in the flare range from 4 to 12% is quite good, clearly indicating an offset of about 3%. The origin of this offset is attributed to the presence of DUV light. An experimental estimate of the DUV component is found in good agreement with the predicted value.

EUV flare and proximity modeling and model-based correction

The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moores law below the 22 nm technology node. EUV lithography will, however, introduce new and unwanted sources of patterning distortions which must be accurately modeled and corrected on the reticle. Flare caused by scattered light in the projection optics is expected to result in several nanometers of on-wafer dimensional variation, if left uncorrected. Previous work by the authors has focused on combinations of model-based and rules-based approaches to modeling and correction of flare in EUV lithography. Current work to be presented here focuses on the development of an all model-based approach to compensation of both flare and proximity effects in EUV lithography. The advantages of such an approach in terms of both model and OPC accuracy will be discussed. In addition, the authors will discuss the benefits and tradeoffs associated with hybrid OPC approaches which mix both rules-based and modelbased OPC. The tradeoffs to be explored include correction time, accuracy, and data volume.

Accurate 3DEMF mask model for full-chip simulation

The Domain Decomposition Method (DDM) for approximating the impact of 3DEMF effects was introduced nearly ten years ago as an approach to deliver good accuracy for rapid simulation of full-chip applications. This approximation, which treats mask edges as independent from one another, provided improved model accuracy over the traditional Kirchhoff thin mask model for the case of alternating aperture phase shift masks which featured severe mask topography. This aggressive PSM technology was not widely deployed in manufacturing, and with the advent of thinner absorbing layers, the impact of mask topography has been relatively well contained through the 32 nm technology node, where Kirchhoff mask models have proved effective. At 20 nm and below, however, the thin mask approximation leads to larger errors, and the DDM model is seen to be effective in providing a more accurate representation of the aerial image. The original DDM model assumes normal incidence, and a subsequent version incorporates signals from oblique angles. As mask dimensions become smaller, the assumption of non-interacting mask edges breaks down, and a further refinement of the model is required to account for edge to edge cross talk. In this study, we evaluate the progression of improvements in modeling mask 3DEMF effects by comparing to rigorous simulation results. It is shown that edge to edge interactions can be accurately accounted for in the modified DDM library. A methodology is presented for the generation of an accurate 3DEMF model library which can be used in full chip OPC correction.

The trade-offs between thin and thick absorbers for EUV photomasks

Through a series of experiments and simulation studies, this paper will explore the lithographic impact of absorber thickness choice on an EUV photomask and highlight the trade-offs that exist between thick and thin absorbers. Fundamentally, thinning the absorber modifies the intensity and phase of light reflected from the absorber while simultaneously decreasing in the influence of feature edge topography. The decision to deploy a thinner absorber depends on which imaging effect has a smaller impact after practical mitigation and correction strategies are employed. These effects and the ability to correct for them are investigated by evaluating the absorber thickness impact on lithographic imaging performance, stray light effects, topography effects, and CD variability. Although various tradeoffs are described, it is generally concluded that thinning the absorber thickness below around 68 nm is not recommended for a TaBN/TaBO absorber stack.

OPC modeling and correction solutions for EUV lithography

The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moores law below the 22nm technology node. EUV lithography will, however, introduce new sources of patterning distortions which must be accurately modeled and corrected with software. Flare caused by scattered light in the projection optics result in pattern density-dependent imaging errors. The combination of non-telecentric reflective optics with reflective reticles results in mask shadowing effects. Reticle absorber materials are likely to have non-zero reflectivity due to a need to balance absorber stack height with minimization of mask shadowing effects. Depending upon placement of adjacent fields on the wafer, reflectivity along their border can result in inter-field imaging effects near the edge of neighboring exposure fields. Finally, there exists the ever-present optical proximity effects caused by diffractionlimited imaging and resist and etch process effects. To enable EUV lithography in production, it is expected that OPC will be called-upon to compensate for most of these effects. With the anticipated small imaging error budgets at sub-22nm nodes it is highly likely that only full model-based OPC solutions will have the required accuracy. The authors will explore the current capabilities of model-based OPC software to model and correct for each of the EUV imaging effects. Modeling, simulation, and correction methodologies will be defined, and experimental results of a full model-based OPC flow for EUV lithography will be presented.

Resist toploss and profile modeling for optical proximity correction applications

Abstract. As critical dimensions decrease for 32-nm node and beyond, the resist loss increases and resist patterns become more vulnerable to etching failures. Traditional optical proximity correction (OPC) models only consider two-dimensional (XY) contours and neglect height (Z) variations. Rigorous resist simulators can simulate a three-dimensional (3-D) resist profile, but they are not fast enough for correction or verification on a full chip. However, resist loss for positive-tone resists is mainly driven by optical intensity variations, which are accurately modeled by the optical portion of an OPC model. We show that a compact resist model can be used to determine resist loss by properly selecting the optical image plane for calibration. The model can then be used to identify toploss hotspots on a full chip and, in some cases, for correction of these patterns. In addition, the article will show how the model can be made more accurate by accounting for some 3-D effects like diffusion through height.

3D mask modeling for EUV lithography

In this work, 3D mask modeling capabilities of Calibre will be used to assess mask topography impact on EUV imaging. The EUV mask absorber height and the non-telecentric illumination at mask level, modulate the captured intensity from the shadowed mask area through the reflective optics on to the wafer, named as the mask shadowing effect. On the other hand, thinning the mask absorber height results in unwanted background intensity, or called flare. A true compromise has to be taken into account for the height parameter of a EUV mask absorber. We will discuss the state-of-the-art 3D mask modeling capabilities, and will present methodologies to tackle the described EUV mask shadowing effect in Calibre software. The findings will be validated against experiments on ASMLs NXE:3100 EUV scanner at imec. Masks with two different absorber heights will be evaluated on various combinations of features containing line/space and contact-hole.

EUV OPC for 56nm metal pitch

For the logic generations of the 15 nm node and beyond, the printing of pitches at 64nm and below are needed. For EUV lithography to replace ArF-based multi-exposure techniques, it is required to print these patterns in a single exposure process. The k1 factor is roughly 0.6 for 64nm pitch at an NA of 0.25, and k1 ≈ 0.52 for 56nm pitch. These k1 numbers are of the same order at which model based OPC was introduced in KrF and ArF lithography a decade or so earlier. While we have done earlier work that used model-based OPC for the 22nm node test devices using EUV,1 we used a simple threshold model without further resist model calibration. For 64 nm pitch at an NA of 0.25, the OPC becomes more important, and at 56nm pitch it becomes critical. For 15 nm node lithography, we resort to a full resist model calibration using tools that were adapted from conventional optical lithography. We use a straight shrink 22 nm test layout to assess post-OPC printability of a metal layer at pitches at 64 nm and 56 nm, and we use this information to correct test layouts.

FinFET-induced anisotropy in printing of implantation shapes

In advanced technological nodes, the photoresist absorbs light, which is reflected by underlying topography during optical lithography of implantation layers. Anti-reflective coating (ARC) helps to suppress the reflections, but ARC removal may damage transistors, not to mention its relatively high cost. Therefore ARC is usually not used, and topography modeling becomes obligatory for printing implantation shapes. Furthermore, presence of Fin Field Effect Transistors (FinFETs) makes modeling of non-uniform substrate reflections exceptionally challenging. In realistic designs, the same implantation shape may be found in a vertical or in a rotated horizontal orientation. This creates two types of relationships between the critical dimension (CD) and FinFET, namely parallel to and perpendicular to the fins. The measurement data shows that CDs differ between these two orientations. This discrepancy is also revealed by our Rigorous Optical Topography simulator. Numerical experiments demonstrate that the shape orientation may introduce CD differences of up to 45 nm with a 248 nm illumination for 14 nm technology. These differences are highly dependent on the enclosure (distance between implantation shape and active area). One of the major causes of the differences is that in the parallel orientation the shape is facing solid sidewalls of fins, while the perpendicular oriented shape “sees” only perforated sidewalls of the fin structure, which reflect much less energy. Meticulously stated numerical experiments helped us to thoroughly understand anisotropic behavior of CD measurement. This allowed us to more accurately account for FinFET-related topography effects in the compact implantation modeling for optical proximity corrections (OPC). This improvement is validated against wafer measurement data.

Resist toploss modeling for OPC applications

As Critical Dimension (CD) sizes decrease for 32 nm node and beyond, resist loss increases and resist patterns become more vulnerable to etching failures. Traditional OPC models only consider 2D contours and neglect height variations. Rigorous resist simulators can simulate a 3D resist profile but they are not fast enough for correction or verification on a full chip. However, resist loss for positive tone resists is mainly driven by optical intensity variations which are accurately modeled by the optical portion of an OPC model. In this article, we show that a CalibreTM CM1 resist model can be used to determine resist loss by properly selecting the optical image plane for calibration. The model can then be used to identify toploss hotspots on a full chip and in some cases to correction of these patterns. In addition, the article will show how the model can be made more accurate by accounting for some 3D effects like diffusion through height.