Steve Bezuk

CuBOL (Cu-column on BOL) technology: A low cost flip chip solution scalable to high I/O density, fine bump pitch and advanced Si-nodes

An innovative packaging solution — ‘Cu-column on BOL’ (CuBOL) is developed that dramatically reduces flip chip package cost and offers superior product reliability, thus posing an important flip chip package solution in mobile product applications. The CuBOL technology, utilizing the fcCuBE™ offering by STATS ChipPAC, entails proprietary changes in the bump interconnect structure using Cu-column bump attached to a narrow trace or bond-on-lead (BOL) on substrate without any solder resist confinement (open SR) in the peripheral I/O region of the die. This enables improved routing efficiency on the substrate top layer thus allowing conversion of a flip chip substrate from original 4L to 2L without compromising functionality. The cost of the flip chip package is lowered by means of reduced substrate layer count, removal of solder on pad (SOP) and solder mask and relaxed design rules. When combined with high density substrate strip design and molded underfill (MUF), this process further lowers the manufacturing cost. Use of Cu-column bump with Pb-free solder cap used in CuBOL technology helps achieve a ‘Green’ package solution, which is complimented by improved package reliability benefits achieved by a remarkable reduction of package stress due to the resulting interconnect structure. The CuBOL technology has also been proven to protect the extreme or ultra low K (ELK/ULK) die-electric against cracking or delamination as confirmed with empirical data generated using advanced silicon node test vehicles and further substantiated by thermo-mechanical simulation results. This paper summarizes the multidisciplinary effort undertaken to develop and qualify CuBOL technology using a 7×7 mm fcTFBGA package as test vehicle (TV). Existing substrate design in a 1–2–1 laminate build-up substrate was comfortably routed into 2 layer substrate design, yet maintaining the I/O count, original bump lay-out & ball map and the original bump-to-ball netlist by applying more efficient routing scheme offered by CuBOL technology. TV wafers were bumped using the composite structure of Cu-column with a Pb-free solder cap. Different aspect ratio of Cu-column height to solder cap height were evaluated to find the optimal one to ensure robust joint formation. Flip chip attach process using composite Cu-column bump with narrow BOL pad was studied in detail in terms of impact of design, and process factors on non-wet, solder short and warpage performance. Side by side comparison of original 4L design and CuBOL 2L was conducted in terms of strip and unit warpage finding significant benefits with the latter. Ultimately, extensive reliability testing was conducted on the packaged units assembled using CuBOL technology by subjecting through a battery of JEDEC standard stress tests for example — preconditioning, temperature cycling (TC), high temperature storage(HTS) and un-biased HAST and excellent reliability results with adequate margins were obtained. Subsequent interception of CuBOL technology into advanced silicon node TVs showed improved package reliability with ELK stress reduction. This finding was further substantiated using thermo-mechanical simulation studies comparing CuBOL interconnect structure with control leg, thus proving CuBOL to be a superior interconnect structure for ELK protection. Finally, electrical performance assessment studies done to ensure product functionality parity between CuBOL design with reduced layer count with the original product design is also presented in this paper.

Proximity Communication flip-chip package with micron chip-to-chip alignment tolerances

As performance gains from scaling silicon slow, improvements in system performance must come from tighter integration. Proximity Communication (PxC) enables designers to aggregate multiple chips that perform as a single large piece of silicon. PxC enables the heterogeneous integration of an optimized mix of process technology and functionality, such as DRAM, Flash memory, and CMOS processor chips. PxC enables silicon die placed face-to-face to communicate using close-field capacitive coupling. In a 90 nm standard CMOS technology, using the packaging techniques described in this paper, PxC provides chip-to-chip latency of 2.5 ns at 4 Gb/s per channel with less than 2.5 mW/Gb/s, an areal bandwidth density of over 2 Tb/smm2, and a BER less than 10−18[1]. In this paper, we describe one of our packaging prototypes that enables PxC and provides its system-level benefits.

A study of wafer level package board level reliability

Board level reliability studies have been performed on wafer level packages (WLP) with various solder ball alloys, underbump metallurgy compositions, and redistribution (RDL) metal thicknesses. All of the WLPs studied pass drop shock with the thicker RDL having the best performance. In contrast to drop shock, thicker RDL did not significantly improve thermal cycle on board reliability. A WLP with no underbump metallurgy (UBM) passed drop shock, but the temperature cycle performance was marginal. A WLP with Ni-doped alloy and NiCu UBM passed drop shock; however, this Ni-rich joint failed temperature cycle.

Evaluation of Ag wire reliability on fine pitch wire bonding

The semiconductor assembly industry has migrated from Au wire to a low-cost alternative, Cu wire, and has recently started increasing the use of Ag alloy wire (Liao et al., 2012). Au wire had long been the standard for manufacturability and reliability but increasing raw material costs has shifted the industry to use Pd-coated Cu (PCC) wire as a new standard. Its use is often seen in the industrys latest fine-pitch wirebond designs. However, the use of Cu wire has some limitations because of its material hardness, especially on die designs requiring a thin Al bond pad thickness (<; 0.7um). In these designs, pad cratering becomes a real concern, and thus Ag wire has found a niche as an alternative low-cost solution to Cu wire. Ag wire is also seen to have similar manufacturability to Au wire. This study focuses on the question of whether 95% Ag alloy wire can be used as an alternative wire interconnection material across a larger portfolio of leading-edge, fine-pitch wirebond designs currently using 18um (0.7mil) Cu wire diameter, with ~46um pad pitch and ~40um bond pad opening (BPO). Two 95% Ag alloy wire compositions were evaluated for reliability performance on both lead frame and laminate-based packages. A dual-row quad-flat no-lead (DRQFN) and BGA package were selected as test vehicles. They both use test die with the same bond pad opening (BPO) size. The results showed that Ag wire could pass thermal cycling (TC) and high temperature storage life (HTSL) tests in both a DRQFN and BGA. However, Ag wire showed a higher failure rate in the BGA than in the DRQFN after highly accelerated stress test (bHAST). A higher Chlorine (Cl) content measured on the laminate substrate was found to correlate with a higher failure rate after bHAST testing on the BGA. Free air ball (FAB) quality was found to be a significant variable on Ag wire bond ability and reliability performance. Poor FAB quality, containing voids and nodes at ball formation, could cause flaws (micro voids) at the Ag-Al bond interface. These flaws at the interface were found to contain high concentrations of Cl, which can result in Al oxide formation and IMC crack post bHAST testing. When comparing the performance of 95% Ag alloy wire from different vendors, it was found that Ag wire with higher Pd content correlated to a reduction of FAB defects and reduced HAST failures. However, for both alloys, no optimized parameters were found that completely eliminated defects below a formed FAB size of 31um. From these results, a clear limitation was found for the use of the 95% Ag alloy wires evaluated, and a minimum bond pad opening for robust Ag wire bond reliability is presented.

Challenges and opportunities of chip package interaction with fine pitch Cu pillar for 28nm

As device dimension shrinks less than 65nm, the propagation delay, crosstalk noises, and power dissipation due to RC (Resistance Capacitance) coupling becomes significant. Cu and LK (Low-k dielectric) material have been introduced to reduce such delays and allow higher device speed and better performance. However, since dielectric material with low-k value usually possesses large amount of porosity, its mechanical properties are degraded significantly which leads to fragile silicon backend structure. This in turn brings in reliability issues like LK cracking due to CPI (Chip Package Interaction). The application of flip-chip packaging introduces significant amount of mechanical stress on BEOL (Back-End-Of-Line) at chip-attach processing step due to CTE mismatch, and makes CPI much more challenging and critical for silicon integration. At advanced technology nodes, increasing performance demand of mobile processors coupled with SoC integration is one major driver of bump pitch reduction [1]. Higher I/O count can be achieved with finer bump pitch since die size very likely stays constant if not shrinking further. Cu pillar and ELK material have been introduced in 28nm to realize the pitch reduction and performance gain. Small UBM structure is required with fine pitch Cu pillar which introduces large amount of stress in BEOL layers. On the other hand, while k-value of ELK is reduced by ~20% compared to LK used in previous technologies, its hardness and mechanical modulus have been reduced by ~30%, resulting in major reduction of ELK material strength. In this paper, we present our key learnings from 28nm CPI development with fine pitch Cu pillar. Empirical data based on CPI TV as well as mechanical stress simulations are discussed. UBM dimension which is a critical factor with Cu pillar from CPI perspective is searched at fine pitch, and our data shows CPI robustness limits pitch reduction with Cu pillar if using standard mass reflow process. ELK robustness is also tested at different process corners, including UBM size, bump height and Cu etching module. Some ELK marginality issues are discovered at certain process corner combinations. CPI margin at 28nm with fine pitch Cu pillar is then assessed by correlating mechanical stress simulation to thermal shock testing data. It is shown that min ~15% ELK margin in terms of max ELK stress is necessary to ensure no ELK delamination happening at process corners. Impact of IMC (Intermetallic Compound) and Ni barrier are also studied. It is found that growth of IMC is critical for ELK integrity with mass reflow process. Once IMC is fully grown between Cu pillar and substrate bonding pad, since its stiffness is 2~3X higher than Lead-free solder, mechanical stress on ELK layers increases dramatically. Additional work is carried out to minimize the growth of IMC. It is confirmed that addition of Ni barrier effectively suppresses IMC growth, and increases CPI margin at process corners by considerable amount. Detailed data is presented and final recommendations on fine pitch Cu pillar conclude the paper.

Electromigration of solder balls for wafer-level packaging with different under bump metallurgy and redistribution layer thickness

Electromigration (EM) has been conducted on lead-free solder balls in wafer-level packages for different redistribution layer (RDL) thicknesses, under bump metallurgy (UBM) schemes, and lead-free solder alloys. Two different types of EM-induced voids were observed at the electron-source side: pancake void between the solder/RDL interface and through-thickness voids in the RDL. In both cases, voids formed at the interface of CuSn intermetallic compound and solder. A Ni-layer in the UBM was found to prolong EM lifetime by slowing the diffusion of Sn into the Cu RDL relative to a Cu-only UBM. The absence of UBM led to the shortest EM lifetime due to direct contact of solder to RDL. Also, a thicker RDL extended lifetime proportionately to the decrease in current density and Joule heating at the critical interface. On the other hand, adding Ni and Ge to the SAC alloy did not statistically impact lifetime.

The impact of different under bump metallurgies and redistribution layers on the electromigration of solder balls for wafer-level packaging

Electromigration performance has been characterized for lead-free solder balls in wafer-level packaging for different solder metallurgy, under bump metallurgy thickness, and redistribution layer thickness and composition. The electromigration lifetimes in this study were found to strongly correlate with the thickness of under bump metallurgy as well as redistribution layer, spanning more than an order-of-magnitude in median time to failure. Also, a redistribution layer comprising of a Ni/Cu bilayer led to a significant lifetime improvement over its Cu-only counterpart, while a change in solder composition did not affect lifetime. Through extensive failure analysis, the differences in lifetimes can be linked to the amount CuSn formation as determined by the under bump metallurgy thickness as well as the location of the CuSn formation as determined by the redistribution layer thickness. Finally, activation energy has been characterized for a process leg with Cu redistribution layer and under bump metallurgy to be 1.34eV, and a current density exponent to be 3.8.

Board level reliability and surface mount assembly of 0.35mm and 0.3mm pitch wafer level packages

Board level reliability studies have been performed on wafer level packages (WLP) on various die sizes with 0.35mm and 0.3mm ball pitches. The 0.35mm pitch test vehicles included 4mm × 4mm, 5mm × 5mm, and 6mm × 6mm package sizes. The 0.3mm pitch test vehicles were 3mm × 3mm and 4mm × 4mm. All test vehicles were fully populated ball arrays. The parts were assembled at 2 different suppliers. All of the WLPs studied passed drop shock. All of the test vehicles passed board level temperature cycle initially except for the 6mm × 6mm. The SMT process optimization included variations of stencil aperture ratios. These modifications impacted temperature cycling reliability. The reliability of the largest package size was improved from this optimization.

Chip Package Interaction with fine pitch Cu pillar bump using mass reflow and thermal compression bonding assembly process for 20nm/16nm and beyond

This paper summarizes key learnings on 20/16nm CPI (Chip-Package-Interaction) challenges at 100um pitch and below to support ever increasing performance/cost/form factor demands for high performance mobile SoCs. CPI solutions for two types of Cu pillar interconnects using mass reflow and thermal compression type assembly process respectively are studied in technology development/production, and separate bump cell structures are proposed.

Quantifying impact of design parameters on Ultra-Low k ILD reliability in fine pitch Cu bump interconnect structures

Increasing feature integration into mobile processors and high performance require denser IO as well as more power/ground pin count. Specifically DDR speed is one of the major drivers for more IO which is realized by aggressively reducing bump pitch. Cu interconnect as well as ULK (Ultra-Low k) dielectric is introduced for such fine pitch processors at advanced Silicon nodes, and the reliability of ULK dielectric is the key concern of CPI (Chip Package Interaction). Since the bump cell size has to be reduced at fine pitch, the thermal-mechanical stress in ULK due to packaging assembly process increases significantly. Robust CPI solutions that address ULK reliability have to be defined at each Si technology node with sufficient margin to cover process variations and provide design flexibility. In this paper, we summarize our findings about impacts of design parameters on ULK reliability. First, since the mechanical stress is approximately inversely proportional to unit bump cell size, experimental study is carried out with various bump cell size at process corner conditions. Bump cell with circular shaped UBM that meets both assembly and CPI requirements without adversely affecting the design space is successfully developed for fine pitch applications. Our data shows reducing bump cell size further will increase CPI risk significantly, and may not be suitable for certain package configurations. Second, bump cell with non-circular shaped UBM is investigated to meet even tighter fine pitch requirement. Data suggests it is critical to understand the ULK reliability impact of both bump cell size as well as orientation of UBM major axis due to its non-circular shape. It is found that, with proper design guidelines, non-circularshaped bump cell can greatly improve CPI margin compared to circular-shaped ones. Third, impact of bump density and die size are studied using thermal shock testing and numerical simulation. It is found that, at design stage, global as well as local UBM density near die corner and periphery area must be carefully considered to prevent any ULK delamination. Impact of die size due to DNP effect is also discussed. Numerical simulation is used in this paper to simulate mechanical stress in ULK dielectric material during packaging assembly process. It is necessary to include Si BEOL stackup, correct material properties and detailed Cu bump interconnect structures in the model for accuracy. However, due to the complexity and length-scale range of BEOL stackup, it is not possible to capture all the details in numerical models. Assumptions and simplifications must be made in the model on various geometry and material parameters including BEOL stackup. Metal, oxide as well aspassivation layer properties need to be smeared using composite material principles. Different material and metal/ILD layer homogenization techniques of BEOL are tested numerically in this work. A paper study comparing mechanical stress of two different BEOL stackup using those homogenization techniques is presented. Further, impact of BEOL metal layers on ULK reliability is studied using simulation, and overall trend is summarized.