Christoph Henkel

A Graphene-Based Hot Electron Transistor

We experimentally demonstrate DC functionality of graphene-based hot electron transistors, which we call graphene base transistors (GBT). The fabrication scheme is potentially compatible with silicon technology and can be carried out at the wafer scale with standard silicon technology. The state of the GBTs can be switched by a potential applied to the transistor base, which is made of graphene. Transfer characteristics of the GBTs show ON/OFF current ratios exceeding 10(4).

Atomic layer deposition of ZrO2/La2O3 high-k dielectrics on germanium reaching 0.5 nm equivalent oxide thickness

We investigate ultrathin ZrO2/La2O3 high-k dielectric stacks on germanium grown by atomic layer deposition. La2O3 is deposited from tris(N,N′-diisopropylformamidinate)-lanthanum and oxygen. Interfacial layer-free oxide stacks with a relative dielectric constant of 21 and equivalent oxide thickness values as low as 0.5 nm are obtained. Metal oxide semiconductor capacitors with platinum as the gate electrode exhibit well-behaved capacitance-voltage characteristics, gate leakage current densities in the range of 0.01–1 A/cm2, and interface trap densities in the range of ∼3×1012 eV−1 cm−2.

Atomic layer-deposited platinum in high-k/metal gate stacks

Nanoscale platinum films are deposited by atomic layer deposition using trimethyl-methylcyclopentadienyl-platinum and oxygen as precursors on the high-k dielectrics ZrO2 and Al2O3, respectively, and on SiO2, issuing deposition temperature and precursor ratios. The ALD-grown platinum films are polycrystalline and show a preferential (1 1 1) orientation. The films are homogeneous with a root mean square roughness of 0.6–0.7 nm and reveal a low resistivity of 13.2 µΩ cm. The effective work functions are 4.76 eV for ZrO2, 5.22 eV for Al2O3 and 5.52 eV for SiO2. It is remarkable that the deposition temperature of the platinum metal gate influences the final equivalent oxide thickness. Comparing both, PVD and ALD platinum films, a decreased leakage current density is observed for the ALD films depending on ALD process conditions, along with an increase in the equivalent oxide thickness.

A manufacturable process integration approach for graphene devices

We experimentally demonstrate DC functionality of graphene-based hot electron transistors, which we call Graphene Base Transistors (GBT). The fabrication scheme is potentially compatible with silicon technology and can be carried out at the wafer scale with standard silicon technology. The state of the GBTs can be switched by a potential applied to the transistor base, which is made of graphene. Transfer characteristics of the GBTs show ON/OFF current ratios exceeding 50.000.

Pt-assisted oxidation of (100)-Ge/high-k interfaces and improvement of their electrical quality

We report on the improvement of electrical quality of (100)-Ge/high-k-dielectric interfaces by introducing thin Pt top layers on the dielectric and subsequent oxidative treatments or using a Pt-deposition process with inherent oxidative components. Here, deposition of thin physical vapor deposition-Pt layers, combined with subsequent oxygen treatments, or oxygen assisted atomic layer deposition of Pt on these dielectrics, is applied. Strong reduction of interface trap densities down to mid-1011 eV−1 cm−2 is achieved. The approach is shown for Pt/ZrO2/La2O3/Ge, Pt/ZrO2/GeO2/Ge, and Pt/ZrO2/Ge gate stacks. By x-ray photoelectron spectroscopy evidence is given for oxygen enrichment at Ge/high-k-dielectric interfaces, to be responsible for the improved electrical properties.

Thulium Silicate Interfacial Layer for Scalable High-k/Metal Gate Stacks

Interfacial layer (IL) control in high-k/metal gate stacks is crucial in achieving good interface quality, mobility, and reliability. A process is developed for the formation of a thulium silicate IL that can be integrated as a replacement for conventional chemical oxide ILs in gate-last high-k/metal gate CMOS process. A straightforward process integration scheme for thulium silicate IL is demonstrated, based on self-limiting silicate formation in inert gas atmosphere and with good selectivity of the etching step. The thulium silicate IL is shown to provide 0.25±0.15 nm equivalent oxide thickness of the IL while preserving excellent electrical quality of the interface with Si. An interface state density ~0.7-2×1011 cm-2eV-1 was obtained at flat-band condition, and the nFET and pFET subthreshold slopes were 70 mV/dec. The inversion layer mobility was 20% higher than for the reference SiOx/HfO2 gate stack. Specifically, the measured mobility values were 230 cm2/Vs for nFET and 60 cm2/Vs for pFET devices, at an inversion charge density of 1013 cm-2 and at a total capacitance equivalent thickness of 1.6 nm.

Process temperature dependent high frequency capacitance-voltage response of ZrO2/GeO2/germanium capacitors

ZrO2/GeO2 dielectrics are grown on germanium substrates by Atomic Layer Deposition (ALD) at substrate temperatures of 150, 200, and 250 °C, respectively. The impact of the deposition temperature on the electrical and structural properties of MOS capacitors is investigated. A significant influence of the ALD temperature on the high frequency capacitance in inversion can be observed, resulting in a shift of the minority carrier response time from 1.15 to 0.2 μs. Time-of-flight secondary ion mass spectroscopy investigations indicate a distinctive depletion of interfacial GeO at higher ALD temperatures, which give rise to trap levels near the oxide/Ge interface.

Ge p-MOSFETs With Scaled ALD

Dielectric thin films of La₂O₃/ZrO₂ deposited by atomic layer deposition (ALD) are investigated to be employed in Ge Schottky barrier p-MOSFETs. La₂O₃ is used as a thin passivation layer and is capped by atomic-layer-deposited ZrO₂ as a gate dielectric. As the gate contact TiN capped by W is applied, midgap-level trap densities of ~ 3-4 × 10¹² eV^-1 cm^-2 and subtreshold slopes down to 115-120 mV/dec are achieved. The devices show negative threshold voltages of -0.5 to -0.6 V, as well as peak hole mobility values of ~ 50-75 cm²/V · s. Equivalent oxide thickness (EOT) is reduced to 0.96 nm upon postmetallization annealing without degrading the interface properties. The results show the scaling potential of the ALD La₂O₃ interlayer capped with ZrO₂ gate dielectrics for the integration into sub-1-nm EOT Ge p-MOSFET devices.

\hbox{La}_{2} \hbox{O}_{3}/\hbox{ZrO}_{2}

In this letter, we demonstrate the simultaneous vertical integration of self-contacting and highly oriented nanowires (NWs) into airbridge structures, which have been developed into surround gated metal oxide semiconductor field effect transistors (MOSFETs). With the use of conventional photolithography, reactive ion etching (RIE), and low pressure chemical vapor deposition, a suspended vertical NW architecture is formed on a silicon on insulator (SOI) substrate where the nanodevice will later be fabricated on. The vapor-liquid-solid (VLS) grown Si-NWs are contacted to prepatterned airbridges by a self-aligned process, and there is no need for postgrowth NW assembly or alignment. Such vertical NW architecture can be easily integrated into existing ICs processes opening the path to a new generation of nonconventional nano devices. To demonstrate the potential of this method, surround gated vertical MOSFETs have been fabricated with a highly simplified integration scheme combining top-down and bottom-up approaches, but in the same way, one can think about the realization of integrated nano sensors on the industrial scale.

Gate Dielectrics

In this work, we demonstrate an approach to tune the electrical behavior of our Ω-gated germanium-nanowire (Ge-NW) MOSFETs by focused ion beam (FIB) implantation. For the MOSFETs, 35 nm thick Ge-NWs are covered by atomic layer deposition (ALD) of a high-κ gate dielectric. With the Ω-shaped metal gate acting as implantation mask, highly doped source/drain (S/D) contacts are formed in a self-aligned process by FIB implantation. Notably, without any dopant activation by annealing, the devices exhibit more than three orders of magnitude higher I(ON) currents, an improved I(ON)/I(OFF) ratio, a higher mobility and a reduced subthreshold slope of 140 mV/decade compared to identical Ge-NW MOSFETs without FIB implantation.