Gunnar Malm

SB-MOSFETs in UTB-SOI Featuring PtSi Source/Drain With Dopant Segregation

MOSFETs of both polarities with PtSi-based Schottky-barrier source/drain (S/D) have been fabricated in ultrathin-body Si-on-insulator. The PtSi is formed in the S/D regions without lateral silicide growth under the gate spacers. This design leads to a 30-nm underlap between the PtSi-Si contacts and the gate edges resulting in low drive currents. Despite the underlap, excellent performance is achieved for both types of MOSFETs with large drive currents and low leakage by means of dopant segregation through As and B implantation into the PtSi followed by drive-in annealing at low temperatures.

Carrier transport through a dry-etched InP-based two-dimensional photonic crystal

The electrical conduction across a two-dimensional photonic crystal (PhC) fabricated by Ar/Cl-2 chemically assisted ion beam etching in n-doped InP is influenced by the surface potential of the hol ...

Hole effective mass in silicon inversion layers with different substrate orientations and channel directions

We explore the possibility to define an effective mass parameter to describe hole transport in inversion layers in bulk MOSFETs and silicon-on-insulator devices. To do so, we employ an accurate and computationally efficient self-consistent simulator based on the six-band k·p model. The valence band structure is computed for different substrate orientations and silicon layer thicknesses and is then characterized through the calculation of different effective masses taking account of the channel direction. The effective masses for quantization and density of states are extracted from the computed energy levels and subband populations, respectively. For the transport mass, a weighted averaging procedure is introduced and justified by comparing the results with hole mobility from experiments and simulations.

Area- and efficiency-optimized junction termination for a 5.6 kV SiC BJT process with low ON-resistance

Implantation-free mesa-etched 4H-SiC bipolar junction transistors (BJTs) with a near-ideal breakdown voltage of 5.6 kV (about 92% of the theoretical value) are fabricated, measured and analyzed by device simulation. An efficient and optimized termination; area-optimized three-zone junction termination extension (O-JTE) is implemented, reducing the total area (and substrate cost) by about 30% compared to the traditional JTE designs. A maximum current gain of β = 44 at a current density of 472 A/cm², and a specific on-resistance of R_ON = 18.8 mΩ.cm² is obtained for the device. The device shows a negative temperature coefficient of the current gain (β = 14.5 at 200 °C) and a positive temperature coefficient of on-resistance (R_ON = 57.3 mΩ·cm² at 200 °C).

Fully etched grating couplers for atomic layer deposited horizontal slot waveguides

Compact broadband grating couplers are designed and studied utilizing Atomic Layer Deposited Horizontal Slot waveguides, with four well-known material layers as the slot. Fabrication process conditions are experimentally studied to obtain more optimized designs. With the precision of the film thickness and refractive index provided by ALD, fabrication of reproducible grating couplers is feasible. An overview of design guidelines regarding the slot size and slot material is provided by 2D Finite Element Method calculations.

Conductivity modulated on-axis 4H-SiC 10+ kV PiN diodes

Degradation-free ultrahigh-voltage (>10 kV) PiN diodes using on-axis 4H-SiC with low forward voltage drop (V_F = 3.3 V at 100 A/cm²) and low differential on-resistance (R_ON = 3.4 mΩ.cm²) are fabricated, measured, and analyzed by device simulation. The devices show stable on-state characteristics over a broad temperature range up to 300 °C. They show no breakdown up to 10 kV, i.e., the highest blocking capability for 4H-SiC devices using on-axis to date. The minority carrier lifetime (τ_P) is measured after epitaxial growth by time resolved photoluminescence (TRPL) technique at room temperature. The τ_P is measured again after device fabrication by open circuit voltage decay (OCVD) up to 500 K.

Fabrication and characterisation of strained Si heterojunction bipolar transistors on virtual substrates

Strained Si HBTs have been demonstrated for the first time with a maximum current gain (beta) of 3700 using a relaxed Si0.85Ge0.15 virtual substrate, Si0.7Ge0.3 base and strained Si emitter. This represents 10times and 27times larger gain compared with pseudomorphic SiGe HBTs and Si control BJTs which were manufactured in parallel and had current gains of 334 and 135, respectively. The strained Si HBTs exhibited satisfactory breakdown voltage (2.5 V) compared with SiGe HBTs (2.7 V) and Si BJTs (4.5 V) and excellent control of collector off-state leakage (< 20 fA).

Electrical conduction through a 2D InP-based photonic crystal

This work investigates the current transport across two-dimensional PhCs dry etched into InP-based low-index-contrast vertical structures using Ar/Cl2 chemically assisted ion beam etching. The electrical conduction through the PhC field is influenced by the surface potential at the hole sidewalls, which is modified by dry etching. The measured current-voltage (I-V) characteristics are linear before but show a current saturation at higher voltages. This behaviour is confirmed by simulations performed by ISE-TCAD software. We investigate the dependence of the conductance of the PhC area as a function of the geometry of the photonic crystal as well as the material parameters. By comparing the experimental and simulated conductance of the PhC, we deduce that the Fermi level is pinned at 0.1 eV below the conduction band edge. The method presented here can be used for evaluating etching processes and surface passivation methods. It is also applicable for other material systems and sheds new light on current driven PhC tuning.

Low loss high-k slot waveguides for silicon photonics

Silicon photonic integrated circuits are promising solutions for high speed on-chip data communication. Producing crystalline silicon optical waveguides at the backend of the IC process flow requires wafer-bonding and a deep substrate etching of an SOI wafer. Fabrication of optical interconnects is less complex and more cost effective if deposited amorphous silicon can be used instead. Amorphous silicon on the other hand suffers from a high absorption. Slot waveguide is a suitable solution for integration of alternative materials with silicon waveguides. Active devices with slot waveguides have been reported by Ramirez et al where the slot layer is doped with rare-earth metals to generate light. In this work successful fabrication and characterization of CMOS compatible low loss high-k amorphous silicon slot waveguides is reported.

Double slot high-k waveguide grating couplers for silicon photonics

Fully etched grating couplers are manufactured for double slot high-k waveguides. These couplers have a maximum efficiency of 22 %. This higher achieved efficiency despite the lack of a matching fluid compared to the case of single slots (18.5 % ) is due to the higher confinement of the optical power in the slot region for the double slot structures. Doubling the slot number reduces the effective refractive index from 2.7 to 2.2.