Christoph Kleint

Nanoscale epitaxial cobalt salicide bitlines for charge trapping memory cells

An epitaxial CoSi2 process is presented, which allows the self-aligned formation of bitlines with only a few tens of nanometer width for Twin Flash memory cells in the 63nm generation. The bitlines show a good thermal stability and low resistance for widths down to 35nm, where polycrystalline CoSi2 is known to exhibit a strong narrow linewidth effect. Transmission electron microscopy studies revealed a cube-on-cube epitaxy with only a few twins depending on the annealing conditions. The low bitline resistance results in a linear drain voltage dependence of the programing characteristics and a suppression of secondary electron injection during programing.

Localized Charge Trapping Memory Cells in a 63 nm Generation with Nanoscale Epitaxial Cobalt Salicide Buried Bitlines

A 63nm Twin Flash memory cell with a size of 0.0225μm 2 per 2 (or 4) bits is presented. To achieve small cell areas, a buried bit line and an aggressive gate length of 100 nm are the key features of this cell together with a minimum thermal budget processing. A novel epitaxial CoSi 2 process allows the salicidation of local buried bitlines with only a few tens of nanometer width.