Torsten Mueller

The Future of Charge Trapping Memories

Floating gate memory cells running into scaling limitations caused by reduced gate coupling and excessive floating gate interference, charge trapping in its two variants multi bit charge trapping and charge trapping NAND is the most promising technology for the mid term. For NOR type applications also phase change RAM could appear as a competitor in a few years, but some considerable development is still down the road. Concepts to challenge NAND type applications are still in the early stage. Therefore charge trapping is expected to be the technology of choice for code storage in the short to mid term and for data storage in the mid term timeframe.

Metal control gate for sub-30nm floating gate NAND memory

This paper investigates the use of a metal control gate for sub 30 nm NAND flash memory. It is shown that polysilicon control gates are not effective at reduced feature sizes due to poor electrical conductivity. As the physical dimensions scale and the doping level of the polysilicon decreases, especially at the beginning of polysilicon deposition, the control gate plugs become electrically non-functional. This isThis paper investigates the use of a metal control gate for sub 30 nm NAND Flash memory. It is shown that polysilicon control gates are not effective at reduced feature sizes due to poor electrical conductivity. As the physical dimensions scale and the doping level of the polysilicon decreases, especially at the beginning of polysilicon deposition, the control gate plugs become electrically non-functional. This is very critical in the narrow control gate plug where the polysilicon can become depleted. A TiN control gate is proposed and implemented in a 48 nm technology. It is shown to eliminate the depletion effect and to have comparable electrical results to a polysilicon control cell. very critical in the narrow control gate plug where the polysilicon can become depleted. A TiN control gate is proposed and implemented in a 48 nm technology. It is shown to eliminate the depletion effect and to have comparable electrical results to a polysilicon control cell.

Nanoscale epitaxial cobalt salicide bitlines for charge trapping memory cells

An epitaxial CoSi2 process is presented, which allows the self-aligned formation of bitlines with only a few tens of nanometer width for Twin Flash memory cells in the 63nm generation. The bitlines show a good thermal stability and low resistance for widths down to 35nm, where polycrystalline CoSi2 is known to exhibit a strong narrow linewidth effect. Transmission electron microscopy studies revealed a cube-on-cube epitaxy with only a few twins depending on the annealing conditions. The low bitline resistance results in a linear drain voltage dependence of the programing characteristics and a suppression of secondary electron injection during programing.

Localized Charge Trapping Memory Cells in a 63 nm Generation with Nanoscale Epitaxial Cobalt Salicide Buried Bitlines

A 63nm Twin Flash memory cell with a size of 0.0225μm 2 per 2 (or 4) bits is presented. To achieve small cell areas, a buried bit line and an aggressive gate length of 100 nm are the key features of this cell together with a minimum thermal budget processing. A novel epitaxial CoSi 2 process allows the salicidation of local buried bitlines with only a few tens of nanometer width.