Nicolas Nagel

The Future of Charge Trapping Memories

Floating gate memory cells running into scaling limitations caused by reduced gate coupling and excessive floating gate interference, charge trapping in its two variants multi bit charge trapping and charge trapping NAND is the most promising technology for the mid term. For NOR type applications also phase change RAM could appear as a competitor in a few years, but some considerable development is still down the road. Concepts to challenge NAND type applications are still in the early stage. Therefore charge trapping is expected to be the technology of choice for code storage in the short to mid term and for data storage in the mid term timeframe.

Nanoscale epitaxial cobalt salicide bitlines for charge trapping memory cells

An epitaxial CoSi2 process is presented, which allows the self-aligned formation of bitlines with only a few tens of nanometer width for Twin Flash memory cells in the 63nm generation. The bitlines show a good thermal stability and low resistance for widths down to 35nm, where polycrystalline CoSi2 is known to exhibit a strong narrow linewidth effect. Transmission electron microscopy studies revealed a cube-on-cube epitaxy with only a few twins depending on the annealing conditions. The low bitline resistance results in a linear drain voltage dependence of the programing characteristics and a suppression of secondary electron injection during programing.

Future trends in charge trapping memories

Charge trapping memories offer advantages for scaling data flash memories in the sub 50nm groundrule. This paper reviews the progress of the main concepts in charge trapping, NROM and SONOS. Both have undergone significant new developments, like the 4 bits/cell for the NROM and the introduction of new materials for SONOS and new cell structures, e.g. including Fin-Fets. Depending on the progress during the next years these concepts will be even more able to compete with the still dominating floating gate techniques

A New Twin Flash Cell for 2 and 4 Bit Operation at 63nm Feature Size

A 63nm Twin Flash memory cell with a size of 0.0225 mum2 / 2 (4) bits is presented. The cell is proposed for data Flash products with 4 to 16 Gbit densities. To achieve small cell areas, a buried bit line and an aggressive gate length of ~100 nm are the key features of this 63nm Twin Flash cell. The cell is well capable of 2 and 4 bit operation.

Localized Charge Trapping Memory Cells in a 63 nm Generation with Nanoscale Epitaxial Cobalt Salicide Buried Bitlines

A 63nm Twin Flash memory cell with a size of 0.0225μm 2 per 2 (or 4) bits is presented. To achieve small cell areas, a buried bit line and an aggressive gate length of 100 nm are the key features of this cell together with a minimum thermal budget processing. A novel epitaxial CoSi 2 process allows the salicidation of local buried bitlines with only a few tens of nanometer width.