Gregory Di Pendina

Spin Orbit Torque Non-Volatile Flip-Flop for High Speed and Low Energy Applications

A novel nonvolatile flip-flop based on spin-orbit torque magnetic tunnel junctions (SOT-MTJs) is proposed for fast and ultralow energy applications. A case study of this nonvolatile flip-flop is considered. In addition to the independence between writing and reading paths, which offers a high reliability, the low resistive writing path performs high-speed, and energy-efficient WRITE operation. We compare the SOT-MTJ performances metrics with the spin transfer torque (STT)-MTJ. Based on accurate compact models, simulation results show an improvement, which attains 20× in terms of WRITE energy per bit cell. At the same writing current and supply voltage, the SOT-MTJ achieves a writing frequency 4× higher than the STT-MTJ.

Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing

This paper deals with a new MRAM technology whose writing scheme relies on the Spin Orbit Torque (SOT). Compared to Spin Transfer Torque (STT) MRAM, it offers a very fast switching, a quasi-infinite endurance and improves the reliability by solving the issue of “read disturb”, thanks to separate reading and writing paths. These properties allow introducing SOT at all-levels of the memory hierarchy of systems and adressing applications which could not be easily implemented by STT-MRAM. We present this emerging technology and a full design framework, allowing to design and simulate hybrid CMOS/SOT complex circuits at any level of abstraction, from device to system. The results obtained are very promising and show that this technology leads to a reduced power consumption of circuits without notable penalty in terms of performance.

Compact Modeling of a Magnetic Tunnel Junction Based on Spin Orbit Torque

High endurance, high speed, scalability, low voltage, and CMOS-compatibility are the ideal attributes of memories that any integrated circuit designer dreams about. Adding non-volatility to all these features makes the magnetic tunnel junctions (MTJs) an ultimate candidate to efficiently build a hybrid MTJ/CMOS technology. Two-terminal MTJs based on spin-transfer torque (STT) switching have been intensively investigated in literature with a variety of model proposals. Despite the attractive potential of the STT devices, the issue of the common writing/reading path decreases their reliability dramatically. A three-terminal MTJ based on the spin-orbit torque (SOT) approach represents a pioneering way to triumph over current two-terminal MTJs by separating the reading and the writing paths. In this paper, we introduce the first compact model, which describes the SOT-MTJ device based on recently fabricated samples. The model has been developed in Verilog-A language, implemented on Cadence Virtuoso platform and validated with Spectre simulator. For optimized simulation accuracy, many experimental parameters are included in this model. Simulations prove the capability of the model to be efficiently used to design hybrid MTJ/CMOS circuits. Innovative logic circuits based on the SOT-MTJ device, modeled in this paper, are already in progress.

Beyond STT-MRAM, Spin Orbit Torque RAM SOT-MRAM for High Speed and High Reliability Applications

For 40 years, microelectronics has been following the Moore’s law, stating that the density and speed of integrated circuits would double every 18 months. However, this trend is presently getting out of breath, because of incoming insurmountable physical limits. Due to decreasing devices size, leakage current is becoming the main contributor to power dissipation of CMOS. Furthermore, the increased density and reduction in die size lead to heat dissipation and reliability issues. Moreover, the dynamic power keeps on growing up with both clock frequency and global capacitance while the power supply is not scaled down accordingly. Several solutions are investigated to try to push forward these limits at technology, circuit or architecture levels. The “more than Moore” concept consists in using new devices beside or in replacement of standard CMOS transistors. For instance, the use of non-volatile devices is seen as a promising solution to reduce power consumption, improve reliability and offer new functionalities. Several technologies are intensively investigated like Phase Change Random Access Memory (PCRAM), Ferroelectric RAM (FeRAM), RedoxRAM (ReRAM) and Magnetic RAM (MRAM). In its 2010 report, ITRS identified RedoxRAM and STT-MRAM as the two most promising technologies for embedded memories at technology nodes below 16 nm. The combination of non-volatility, fast access time and endurance in MRAM technology paves the path toward a universal memory. Although an expanding attention is given to two-terminal Magnetic Tunnel Junctions (MTJ) with writing based on Spin-Transfer Torque (STT) switching as the potential candidate for future memories, it suffers from weaknesses. Indeed, two main shortcomings are still limiting the reliability and endurance of STT-MRAMs: i) The high current density required for writing can occasionally damage the MTJ barrier, specially for switching on the nanosecond time scale ii) It remains a challenge to fulfill a reliable reading without ever causing switching for very advanced technology nodes, since writing and reading operations share the same path, through the junction. Indeed, the smaller the MTJ the lower the writing current without having the possibility to reduce the reading current to maintain a reliable sensing. Three-terminal MTJ with writing based on Spin-Orbit Torque (SOT) approach revitalizes the hope of an ultimate RAM. It represents a pioneering way to triumph over current two-terminal MTJ’s limitations by separating the reading and the writing paths, completely avoiding tunnel barrier damaging and read disturb issues.

Non-volatile FPGAs based on spintronic devices

This paper presents an innovative architecture for radiation-hardened FPGA (Field Programmable Gate Array). This architecture is based on the use of MTJs (Magnetic Tunnel Junctions), magnetic nanostructures used as basic elements of MRAM (Magnetic Random Access Memory). These devices are totally immune to radiations and can be used as a reference memory to perform “scrubbing” techniques, which consist in regularly reloading the configuration of the FPGA to fix the radiation induced errors that may have occured. This approach allows hardening the circuits at low cost in terms of area, while reducing the standby power consumption and offering new functionalities, like dynamic reconfiguration. A silicon demonstrator was implemented, including a 2-inputs LUT (Look Up Table) and tested using a digital tester, giving encouraging results.

Ultra compact non-volatile flip-flop for low power digital circuits based on hybrid CMOS/magnetic technology

Complex systems are mainly integrated in CMOS technology, facing issues in advanced process nodes, in particular for power consumption and heat dissipation. Magnetic devices such as Magnetic Tunnel Junction (MTJ) have specific features: non-volatility, high cyclability (over 1016) and immunity to radiations. Combined with CMOS devices they offer specific and new features to designs. Indeed, the emerging hybrid CMOS/Magnetic process allows integrating magnetic devices within digital circuits, modifying the current architectures, in order to contribute to solve the CMOS process issues. We present a high performance innovative non-volatile latch integrated into a flipflop which can operate at high speed. It can be used to design non-volatile logic circuits with ultra low-power consumption and new functionalities such as instant startup. This new flip-flop is integrated as a standard cell in a full Magnetic Process Design Kit (MPDK) allowing full custom and digital design of hybrid CMOS/Magnetic circuits using standard design tools.

Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories

The most widely used embedded memory technology, static random access memory (SRAM), is heading toward scaling problems in advanced technology nodes due to the leakage currents caused by the quantum tunneling effect. As an alternative, spin-transfer torque magnetic RAM (STT-MRAM) technology shows comparable performance in terms of speed and power consumption and much better performance in terms of density and leakage. Moreover, MRAM brings up new paradigms in system design thanks to its inherent nonvolatility, which allows the definition of new instant-on/off policies and leakage current optimization. Based on our compact model, we have developed a fully characterized system-on-chip from the basic cell up to the system architecture in a 40nm LP hybrid CMOS/magnetic process. Through simulations, first we demonstrate that STT-MRAM is a candidate for the memory part of embedded systems, and second we implement a check-pointing methodology based on the regular interrupt routines of a processor to enable a fast power on and off functionality. Using a synthetic benchmark developed in high-level programming languages intended to be representative of integer system performance, our method shows that having MRAM instead of SRAM in an embedded design brings up important energy savings. The influence of the check-pointing routine on power consumption is finally evaluated with regard to various shutdown and restart behaviors.

Hybrid CMOS/magnetic Process Design Kit and SOT-based non-volatile standard cell architectures

This paper gives an overview of hybrid CMOS/magnetic logic circuit design. We describe the magnetic devices, the expected advantages of using them beside CMOS to help to circumvent the incoming limits of VLSI circuits and the tools required to design such circuits, including Process Design Kit (PDK) and Standard Cells (SC). As a case of study, we particularly focus on a new and promising device technology based on Spin Orbit Torque (SOT) effect.

GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack

To tackle the key issues of monolithic heterogeneous integration, fast yet low power processing, high integration density, fast yet low power storage, the goal of the GREAT project is to co-integrate multiple functions like sensors (“Sensing”), RF receivers (“Communicating”) and logic/memory (“Processing/Storing”) together within CMOS by adapting the STT-MTJs (Magnetic devices) to a single baseline technology enabling logic, memory, and analog functions in the same System-on-Chip (SoC) as the enabling technology platform for Internet of Things (IoT). This will lead to a unique STT-MTJ cell technology called Multifunctional Standardized Stack (MSS). The major outputs of GREAT are the technology and the architecture platform for IoT SoCs providing better integration of embedded & mobile communication systems and a significant decrease of their power consumption. Based on the STT-MTJs (now viewed as the most suitable technology for digital applications and with a huge potential for analog subsystems) unique set of performances (non-volatility, high speed, infinite endurance and moderate read/write power), GREAT will achieve the same goal as heterogeneous integration of devices but in a much simpler way since the MSS will enable different functions using the same technology.

An SEU tolerant MRAM based non-volatile asynchronous circuit design

Radiation robust circuit design for harsh environments like space is a big challenge for today engineers and researchers. As circuits become more and more complex and CMOS processes get denser and smaller, their immunity towards particle strikes decreases drastically. This work proposes a novel SEU tolerant circuit design based on asynchronous communication coupled with magnetic memory and Silicon on Insulator (SOI) process that can detect and correct single or multiple errors without the triplication of the circuit. The combination of these techniques should give fundamentally higher performance than what is available today in terms of robustness but also in terms of surface area, reliability, speed and power consumption.