Christopher Cork

Double-patterning interactions with wafer processing, optical proximity correction, and physical design flows

In this paper we study interactions of double patterning technology (DPT) with lithography, optical proximity correction (OPC) and physical design flows for the 22-nm device node. DPT methods decompose the original design intent into two individual masking layers, which are each patterned using single exposures and existing 193-nm lithography tools. Double exposure and etch patterning steps create complexity for both process and design flows. DPT decomposition is a critical software step that will be performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of original design intent polygons into multiple polygons, where required, and coloring of the resulting polygons. We evaluate the ability to meet key physical design goals, such as reduce circuit area, minimize relayout effort, ensure DPT compliance, guarantee patterning robustness on individual layer targets, ensure symmetric wafer results, and create uniform wafer density for the individual patterning layers.

Printability verification for double-patterning technology

For keeping pace with Moores Law of reducing the feature sizes on integrated circuits, the driving forces have been reductions in the exposure-tool wavelength, and increases in the lens numerical aperture (NA). With extreme ultra-violet (EUV) lithography and 3rd-generation immersion delayed for production use, these driving forces are now stalled at a wavelength of 193 nm and an NA of 1.35. Therefore, double-patterning technology (DPT) is needed for printing 22 nm device node features. With DPT, a 22 nm layout is split into two patterns. Each pattern is printed using 32 nm node lithography technology, and the original pattern is recovered by a logical summation (the Boolean OR operation) of these two separately exposed patterns. DPT presents several challenges for printability verification. First, the etch target can be very different from the resist target because significant biasing is used to improve the lithography process window. Second, overlaps between the two patterns produce new problems such as sharp-cornered pinching at pattern junctions, and bridging between patterns. Finally, there are additional process variations: misalignment between the two patterns, and twice as many dose and defocus dimensions. We present results from a full-chip DPT-verification tool that addresses these challenges. We also provide examples of lithography problems that are specific to DPT, and describe possible guidance for the resolution enhancement techniques (RET) and design tools.

Calibrating OPC models using asymmetric structures

Good OPC model calibration structures should be representative of and span the dimensions and layout forms that will be found in the product on which the model will be applied. If model fitting is done using edge placement (EPE) methods, only symmetric structures can be used and this constrains the model fitter to a classic but limited set of calibration structures. The most critical features, such as those from a bit cell tend to be asymmetric. While asymmetric structures have typically been used for model verification, using them in model calibration structures provides more degrees of freedom for the calibration test structures to capture two dimensional behavior. This produces more robust, accurate models which yield better quality corrections on wafer. During process development models are re-calibrated as the process is adjusted and optimized. In some cases particularly important critical configurations can be added to the calibration set to insure maximum accuracy on those features. As these configurations are extracted from real designs, they are rarely symmetric. This paper describes how by using a CD-based rather than an edge-placement based modeling approach, OPC models can be created from asymmetric, more product-like type structures, and demonstrates how this can allow better predictability on other verification structures. The paper will also review the two types of model forms commonly used (Constant and Variable Threshold models) and compare their performance while using asymmetric calibration structures.

Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows

In double-patterning technology (DPT), we study the complex interactions of layout creation, physical design and design rule checking flows for the 22nm and 16nm device nodes. Decomposition includes the cutting (splitting) of original design-intent features into new overlapping polygons where required; and the coloring of all the resulting polygons into two mask layouts. We discuss the advantages of geometric distribution for polygon operations with the limited range of influence. Further, we find that even the naturally global coloring step can be handled in a geometrically local manner. We analyze and compare the latest methods for designing, processing and verifying DPT methods including the 22nm and 16nm nodes.

Mathematically describing the target contour in silicon such that model-based OPC can best realize design intent

IC layouts are typically defined with simple shapes such as rectangles and 45° triangles. Fundamental limitations in the imaging process unavoidably prevent the exact rendering of these shapes on the wafer, and this necessitates an interpretation of what should appear on silicon. For example, an OPC tool must interpret a square corner as something more rounded, otherwise the pursuit of the ideal shape may lead to bridging and/or Mask Rule Check (MRC) violations. A solution to this is to move the target points for Optical Proximity Correction (OPC) off from the GDS edges and onto mathematically described curves inscribed within the corners of the design polygon and use these as the target for OPC correction. Suitable values for the radius of these curves depend on the model used, the geometry they are applied to, and the requirements of the device the shape builds. An uncorrected square corner gives a printed contour whose radius of curvature, nearest the design corner, provides a target radius for a low impact OPC correction. Line ends, right angled bends in tracks and end caps all need separate optimization in terms of the best radius of target curve to use. By understanding whether the design priority is for CD control (such as poly gate) or for positional accuracy (such as contact enclosure) the OPC correction parameters and final target shape can be modified in such a way to best realize these interpreted goals.

Large-scale double-patterning compliant layouts for DP engine and design rule development.

Double Patterning is seen as the prime technology to keep Moores law on path while EUV technology is still maturing into production worthiness. As previously seen for alternating-Phase Shift Mask technology[1], layout compliance of double patterning is not trivial [2,3] and blind shrinks of anything but the most simplistic existing layouts, will not be directly suitable for double patterning. Evaluating a production worthy double patterning engine with highly non-compliant layouts would put unrealistic expectations on that engine and provide metrics with poor applicability for eventual large designs. The true production use-case would be for designs that have at least some significant double patterning compliance already enforced at the design stage. With this in mind a set of ASIC design blocks of different sizes and complexities were created that were double patterning compliant. To achieve this, a set of standard cells were generated, which individually and in isolation were double patterning compliant, for multiple layers simultaneously. This was done using the automated Standard Cell creation tool CadabraTM [4]. To create a full ASIC, however, additional constraints were added to make sure compliance would not be broken across the boundaries between standard cells when placed next to each other [5]. These standard cells were then used to create a variety of double patterning compliant ASICs using iCCompilerTM to place the cells correctly. Now with a compliant layout, checks were made to see if the constraints made at the micro level really do ensure a fully compliant layout on the whole chip and if the coloring engine could cope with such large datasets. A production worthy double patterning engine is ideally distributable over multiple processors [6,7] so that fast turn-around time can be achievable on even the largest designs. We demonstrate the degree of linearity of scaling achievable with our double patterning engine. These results can be understood together with metrics such as the distribution of the sizes of networks requiring coloring resulting from these designs.

Proximity correction of IC layouts using scanner fingerprints

The availability of a precise physical description of the imaging system that was used to expose an OPC calibration tests pattern is now possible. This data is available from scanner manufacturers of the tool as built and also by scanner self-metrology in the Fab at any time. This information reduces significant uncertainty when regressing a model used for OPC and allows the creation of more accurate models with better predictability. This paper explores the considerations necessary for best leveraging this data into the OPC model creation flow.

Accounting for lens aberrations in OPC model calibration

Whenever an OPC calibration wafer is exposed, there will be an unavoidable and perhaps non-representative level of aberration at that part of the exposure field corresponding to where the calibration pattern is written on the mask. In practice these aberrations values will vary across both the field and from exposure tool to exposure tool. The OPC engineer is therefore faced with the question of whether the aberrations specific to this part of the reticle field and hence lens should be taken into account during model fitting. Methodologies have been developed to allow OPC model calibration when the aerial image is asymmetric either due to the test pattern or the aberrations in the lens that lead to this. This will be referred to as asymmetry aware model calibration. These methodologies allow asymmetric test structures to be added to the calibration set to allow greater pattern coverage and therefore allow for a better overall model fit. Asymmetric calibration structures tend also to be particularly sensitive to asymmetric lens aberrations such as Coma. The question becomes whether the calibration fit should include asymmetric structures and hence account for coma, or consider only symmetrical, coma-insensitive structures when doing a model fit. The paper will investigate, using actual model calibration measurement data the suitability of accounting for model coma in an actual OPC model calibration.

Line end design intent estimation using curves

Semiconductor foundries need to have a single, standard mask preparation procedure to deal with the large number of designs they receive. This data is typically of two sorts; the random logic over which they have little control of how the design intent is represented; and cells from dense arrays such as memory, often with design rule violations, whose OPC correction needs to be precisely optimized to achieve best yield and device performance. Occasionally the input data will contain sub-resolvable notches and extensions, which while not violating DRC specifications, would, if filled, result in DRC violations. This may be due to a non DFM aware automated layout tool, or a designer aggressively trying to minimize circuit density. In practice it is worthwhile to clean up these notches to ease OPC correction. Doing this should not result in printability errors as these notches typically represent a more complex curved design intent that cannot be accurately represented due to the restrictions imposed by the limited number of polygon edge directions available for layout. Similarly, memory cell layouts often have significant implied curvature. These may only be corrected properly if the OPC target point is defined precisely for each individual segment. In general, letting the OPC correction engine correct a layout defined by a realistic, curved target shape gives better quality corrections with greater process window. The challenge for the OPC engineer working in a foundry is therefore to determine a clean-up methodology for incoming data and to correctly apply the design intent, where necessary, from the original pre-cleanup data. A programmable OPC engine gives the user flexibility in optimizing the set of rules embedded in the OPC cleanup and correction recipes. These embed within them the algorithms to interpret the rounding on the desired silicon image not only for line-ends and corners of random logic but also the more complex curved silicon images and tolerances required by memory cells.

An investigation into scalability and compliance for triple patterning with stitches for metal 1 at the 14nm node

Lithographers had hoped that single patterning would be enabled at the 20nm node by way of EUV lithography. However, due to delays in EUV readiness, double patterning with 193i lithography is currently relied upon for volume production for the 20nm node’s metal 1 layer. At the 14nm and likely at the 10nm node, LE-LE-LE triple patterning technology (TPT) is one of the favored options [1,2] for patterning local interconnect and Metal 1 layers. While previous research has focused on TPT for contact mask, metal layers offer new challenges and opportunities, in particular the ability to decompose design polygons across more than one mask. The extra flexibility offered by the third mask and ability to leverage polygon stitching both serve to improve compliance. However, ensuring TPT compliance – the task of finding a 3-color mask decomposition for a design – is still a difficult task. Moreover, scalability concerns multiply the difficulty of triple patterning decomposition which is an NP-complete problem. Indeed previous work shows that network sizes above a few thousand nodes or polygons start to take significantly longer times to compute [3], making full chip decomposition for arbitrary layouts impractical. In practice Metal 1 layouts can be considered as two separate problem domains, namely: decomposition of standard cells and decomposition of IP blocks. Standard cells typically include only a few 10’s of polygons and should be amenable to fast decomposition. Successive design iterations should resolve compliance issues and improve packing density. Density improvements are multiplied repeatedly as standard cells are placed multiple times. IP blocks, on the other hand, may involve very large networks. This paper evaluates multiple approaches to triple patterning decomposition for the Metal 1 layer. The benefits of polygon stitching, in particular, the ability to resolve commonly encountered non-compliant layout configurations and improve packing density, are weighed against the increased difficulty in finding an optimized, legal decomposition and coping with the increased scalability challenges.