Gerard Luk-Pat

Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography

Self-aligned double patterning (SADP) lithography is a leading technology for 10nm node Metal layer fabrication. In order to achieve successful decomposition, SADP-compliant design becomes a necessity. Spacer-Is-Dielectric (SID) is the most popular flavor of SADP with higher flexibility in design. This paper makes a careful study on the challenges for SID-compliant detailed routing and proposes a graph model to capture the decomposition violations and SID intrinsic residue issues. Then a negotiated congestion based scheme is adopted to solve the overall routing problem. The proposed SID-compliant detailed routing algorithm simultaneously assigns colors to the routed wires, which provides valuable information guiding SID decomposition. In addition, if one pin has multiple candidate locations, the optimal one will be automatically determined during detailed routing. The decomposability of the conflict-free routing layers produced by our detailed router is verified by a commercial SADP decomposition tool.

Implications of triple patterning for 14nm node design and patterning

The upcoming 14nm logic node will require lithographic patterning of complex layout patterns with minimum pitches of approximately 44nm to 50nm. This requirement is technically feasible by reusing existing 20nm litho-etch-litho-etch (LELE) double patterning (DPT) methods with very strong restricted design rules. However, early indications are that the cost-effective design and patterning of these layouts will require lithographic methods with additional resolution, especially in two-dimensional configurations. If EUV lithography reaches maturity too late, the 14nm logic node will need other lithographic techniques and the corresponding physical design rules and EDA methodologies to be available. Triple patterning technology (TPT) is a strong option for 14nm node logic on both hole and line-space pattern layers. In this paper we study major implications of a 14nm logic TPT lithographic solution upon physical design, design rules, mask synthesis/EDA algorithms and their process interactions.

Design compliance for spacer is dielectric (SID) patterning

Self-Aligned Double Patterning (SADP) is a strong candidate for the lower-Metal layers of the 14 nm node. Compared to Litho-Etch-Litho-Etch (LELE) Double Patterning, SADP has lower LWR (line-width roughness), tighter line-end minimum spacing, and lower sensitivity to overlay errors. However, design for SADP is more restricted than for LELE. This work explores the design of layouts compatible with the Spacer Is Dielectric (SID) flavor of SADP. It is easy to find layouts that are LELE-compliant but not SID-compliant. One reason is that polygon stitching is not allowed in SID. Another is that certain drawn-space values are forbidden in SID. In this paper, we will write down some basic rules for SID-compliant design, and introduce some SID-printing artifacts that may be worrisome.

Double-patterning interactions with wafer processing, optical proximity correction, and physical design flows

In this paper we study interactions of double patterning technology (DPT) with lithography, optical proximity correction (OPC) and physical design flows for the 22-nm device node. DPT methods decompose the original design intent into two individual masking layers, which are each patterned using single exposures and existing 193-nm lithography tools. Double exposure and etch patterning steps create complexity for both process and design flows. DPT decomposition is a critical software step that will be performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of original design intent polygons into multiple polygons, where required, and coloring of the resulting polygons. We evaluate the ability to meet key physical design goals, such as reduce circuit area, minimize relayout effort, ensure DPT compliance, guarantee patterning robustness on individual layer targets, ensure symmetric wafer results, and create uniform wafer density for the individual patterning layers.

Avoiding wafer-print artifacts in spacer is dielectric (SID) patterning

For patterning the upper Metal layers of the 10 nm node, Spacer Is Dielectric (SID) Patterning is the leading candidate. Compared to Litho-Etch-Litho-Etch Double Patterning, SID has lower line-width roughness, tighter line-end spacing, and lower sensitivity to overlay errors. However, SID places more restrictions on design, and creates wafer-printing artifacts or “spurs.” These printing artifacts arise because SID uses a subtractive trim etch to create “negative contours,” which are very different from the positive contours of single-exposure patterning. In this work, we show the origin of these spurs, and present rule-based decomposition methods to avoid or mitigate them.

Printability verification for double-patterning technology

For keeping pace with Moores Law of reducing the feature sizes on integrated circuits, the driving forces have been reductions in the exposure-tool wavelength, and increases in the lens numerical aperture (NA). With extreme ultra-violet (EUV) lithography and 3rd-generation immersion delayed for production use, these driving forces are now stalled at a wavelength of 193 nm and an NA of 1.35. Therefore, double-patterning technology (DPT) is needed for printing 22 nm device node features. With DPT, a 22 nm layout is split into two patterns. Each pattern is printed using 32 nm node lithography technology, and the original pattern is recovered by a logical summation (the Boolean OR operation) of these two separately exposed patterns. DPT presents several challenges for printability verification. First, the etch target can be very different from the resist target because significant biasing is used to improve the lithography process window. Second, overlaps between the two patterns produce new problems such as sharp-cornered pinching at pattern junctions, and bridging between patterns. Finally, there are additional process variations: misalignment between the two patterns, and twice as many dose and defocus dimensions. We present results from a full-chip DPT-verification tool that addresses these challenges. We also provide examples of lithography problems that are specific to DPT, and describe possible guidance for the resolution enhancement techniques (RET) and design tools.

Photomask quality assessment solution for 90-nm technology node

As 90 nm LSI devices are about to enter pre-production, the cost and turn-around time of photomasks for such devices will be key factors for success in device production. Such devices will be manufactured with state-of-the-art 193nm photolithography systems. Photomasks for these devices are being produced with the most advanced equipment, material and processing technologies and yet, quality assurance still remains an issue for volume production. These issues include defect classification and disposition due to the insufficient resolution of the defect inspection system at conventional review and classification processes and to aggressive RETs, uncertainty of the impact the defects have on the printed feature as well as inconsistencies of classical defect specifications as applied in the sub-wavelength era are becoming a serious problem. Simulation-based photomask qualification using the Virtual Stepper System is widely accepted today as a reliable mask quality assessment tool of mask defects for both the 180 nm and 130 nm technology nodes. This study examines the extendibility of the Virtual Stepper System to 90nm technology node. The proposed method of simulation-based mask qualification uses aerial image defect simulation in combination with a next generation DUV inspection system with shorter wavelength (266nm) and small pixel size combined with DUV high-resolution microscope for some defect cases. This paper will present experimental results that prove the applicability for enabling 90nm technology nodes. Both contact and line/space patterns with varies programmed defects on ArF Attenuated PSM will be used. This paper will also address how to make the strategy production-worthy.

Layout optimization with assist features placement by model based rule tables for 2x node random contact

As the industry pushes to ever more complex illumination schemes to increase resolution for next generation memory and logic circuits, sub-resolution assist feature (SRAF) placement requirements become increasingly severe. Therefore device manufacturers are evaluating improvements in SRAF placement algorithms which do not sacrifice main feature (MF) patterning capability. There are known-well several methods to generate SRAF such as Rule based Assist Features (RBAF), Model Based Assist Features (MBAF) and Hybrid Assisted Features combining features of the different algorithms using both RBAF and MBAF. Rule Based Assist Features (RBAF) continue to be deployed, even with the availability of Model Based Assist Features (MBAF) and Inverse Lithography Technology (ILT). Certainly for the 3x nm node, and even at the 2x nm nodes and lower, RBAF is used because it demands less run time and provides better consistency. Since RBAF is needed now and in the future, what is also needed is a faster method to create the AF rule tables. The current method typically involves making masks and printing wafers that contain several experiments, varying the main feature configurations, AF configurations, dose conditions, and defocus conditions – this is a time consuming and expensive process. In addition, as the technology node shrinks, wafer process changes and source shape redesigns occur more frequently, escalating the cost of rule table creation. Furthermore, as the demand on process margin escalates, there is a greater need for multiple rule tables: each tailored to a specific set of main-feature configurations. Model Assisted Rule Tables(MART) creates a set of test patterns, and evaluates the simulated CD at nominal conditions, defocused conditions and off-dose conditions. It also uses lithographic simulation to evaluate the likelihood of AF printing. It then analyzes the simulation data to automatically create AF rule tables. It means that analysis results display the cost of different AF configurations as the space grows between a pair of main features. In summary, model based rule tables method is able to make it much easier to create rule tables, leading to faster rule-table creation and a lower barrier to the creation of more rule tables.

Process window and integration results for full-chip model-based assist-feature placement at the 32 nm node and below

Model-based assist-feature (MBAF) placement has been shown to have considerable lithographic benefits vs. rule-based assist-feature (RBAF) placement for advanced technology-node requirements. For very strong off-axis illumination, MBAF-placement methods offer improved process window, especially for so-called forbidden pitch regions, and greatly simplified tuning of AF-placement parameters. Historically, however, MBAF-placement methods had difficulties with full-chip runtime, friendliness to mask manufacturing (e.g., mask rule checks or MRCs), and methods to ensure that placed AFs do not print on-wafer. Therefore, despite their known limitations, RBAF-placement methods were still the industry de facto solution through the 45 nm technology node. In this paper, we highlight recent manufacturability advances for MBAFs by a detailed comparison of MBAF and RBAF methods. The MBAF method employed uses Inverse Mask Technology (IMT) to optimize AF placement, size, shape, and software runtime, to meet the production requirements of the 28 nm technology node and below. MBAF vs. RBAF results are presented for process window performance, and MBAF vs. OPC results are presented for full-chip runtimes. The final results show that MBAF methods have process-window advantages for technology nodes below 45 nm, with runtimes that are comparable to OPC.

Assist feature aware double patterning decomposition

Double patterning has gained prominence as the most likely lithographic methodology to help keep Moores law going towards 32nm 1/2 pitch lithography. While solutions, to date, have focused mainly on gap splitting to avoid minimum spacing violations, the decomposition should, ideally, also attempt to optimize the process window of the decomposed masks. A major contributor to process window sensitivity is the correct placement of sub-resolvable assist features. These features are placed once the polygons of each mask are defined, i.e. post decomposition. If some awareness of this downstream process step is made available to the double patterning decomposition stage, then a more robust decomposition can be achieved.