Erik Vick

Highly flexible transparent electrodes for organic light-emitting diode-based displays

Multilayer indium-tin-oxide (ITO)–Ag–ITO stacks were evaluated as transparent conductors for flexible organic light-emitting diode (OLED) displays. The ITO–metal–ITO (IMI) samples exhibited significantly reduced sheet resistance over ITO and greater than 80% optical transmission. The IMI films deposited on plastic substrates showed dramatically improved mechanical properties when subjected to bending both as a function of radius of curvature as well as number of cycles to a fixed radius. OLEDs were fabricated on both ITO and IMI anodes, and the devices with IMI anodes showed improved performance at current densities greater than 1mA∕cm2 due to the improved conductivity of the anode.

Development and evaluation of bend‐testing techniques for flexible‐display applications

Abstract— Two different approaches to automated bend testing of flexible substrates for display applications were implemented and characterized: a conventional collapsing radius geometry and a novel technique called the “X-Y-θ” geometry. Indium tin oxide (ITO) coated polymer substrates were used to compare the performance of the two automated systems by in-situ electrical-resistance measurements. Manual bending on fixed-diameter mandrels was used to help interpret the results. The advantages and drawbacks of the two systems for providing information of practical use to flexible display R&D are discussed.

Fabrication of TSV-based silicon interposers

Silicon interposers with through-silicon vias (TSVs) will enable further miniaturization and reduction in power consumption for future electronic systems. The design and method of integration of the TSVs can have a significant effect on the interposer process complexity, yield, and reliability. This paper will compare two different process approaches for Si interposer fabrication. In one approach, TSVs were formed “TSVs last”, following the front-side multi-level metallization (MLM) processing, and were lined with copper, but were not filled. The second approach was a “TSVs first” process in which copper-filled TSVs were formed in silicon wafers prior to frontside MLM processing. These wafers were processed through front-side Cu CMP and back-side wafer thinning, leaving Cu-filled TSVs exposed from both sides. The resulting TSV substrates could then be used for interposer fabrication involving front-side and back-side metal processing. This paper will summarize the fabrication and testing of TSV electrical test structures and interposer wafers using the TSVs-last process. For the TSVs-first process, which is still in development, the paper will review the demonstrations of key process modules and discuss integration and reliability considerations.

Vias-last process technology for thick 2.5D Si interposers

Relative to traditional chip-to-substrate or chip-to-PCB packaging, solutions utilizing 2.5D silicon interposers can provide significantly higher I/O densities, resulting in reduced size, lower power consumption, and higher functionality [1,2]. One example of an advanced packaging application enabled by Si interposers is an embedded computing module (ECM) illustrated in Figure 1. Benefits of this advanced electronic packaging approach include (1) reduction in size by a factor of 2-3, (2) reduction in system power, and (3) elimination of on-die termination resistors [3].

Process integration and testing of TSV Si interposers for 3D integration applications

Two 3D Si interposer demonstration vehicles containing through-Si vias (TSVs) were successfully fabricated using integration of two different TSV formation and multilevel metallization (MLM) process modules. The first Si interposer vehicles were made with a dual damascene frontside MLM (5 levels), backside TSV (unfilled, vias-last), and backside metallization (2 levels) process sequence on standard thickness 6” wafers. The front-side MLM was comprised of 4 metal routing layers (2 μm Cu with 2 μm oxide interlayer dielectric) and 1 metal pad layer. Electrical yield as high as 100% was obtained on contact chain test structures containing 26,400 vias between the front-side MLM layers, while the average contact resistance between the dual damascene levels was <; 4 MΩ per via. TSV dimensions of 100 and 80 μm diameter and 6:1 aspect ratio were investigated. DRIE bottom clear process conditions were optimized for each via dimension to produce 100% yield on TSV contact chains with up to 540 vias. The optimized DRIE conditions also resulted in TSV resistance below 30 MΩ and sufficient TSV isolation resistance (>;100MΩ/via at 3.3V) for the target application. Functional testing of two die (4 cm × 3.7 cm die size) showed that 99% of the functional circuit path nets had acceptable continuity and isolation. The second Si interposer vehicles were fabricated using a vias-first TSV (filled, blind vias), wafer-level packaging (WLP) front-side MLM (2 levels), wafer thinning (via reveal), and WLP-MLM (1 level) process sequence on stock 6” wafers. Via dimensions for the viasfirst interposers were 50 μm diameter × 315 μm depth or 80 μm diameter × 315 μm depth (6:1 or 4:1 aspect ratios). The front and backside MLM was formed with a 2 μm Cu routing layer and one of two spin-on dielectrics (polyimide or ALX) for evaluation of polymer dielectric process compatibility with Cu-filled TSVs and thinned wafer processing. Details of the process modules and process integration required to realize the TSV Si interposers are described.

Advanced 3D mixed-signal processor for infrared focal plane arrays: Fabrication and test

We report successful implementation of high-density 3D integration technology in the fabrication of advanced mixed-signal processors for infrared focal plane arrays. Separate analog and digital integrated circuits (ICs) were custom designed and fabricated in standard bulk CMOS technology in two different commercial foundries. The 3D interconnects were arrayed in a 256×256 format with a 30 micron pitch and had the form of through-silicon vias 4 micron in diameter and 30 micron deep. Completed 3D readout IC stacks were tested pixel by pixel, demonstrating operability of 99.9%. The 3D IC stacks were hybridized with infrared photodiode arrays and produced functional FPA imagers with 99.9% array operability and unprecedented performance. Such imaging arrays and other smart sensors enabled by 3D integration of sensing elements with sophisticated signal processing are of increasing interest for Internet-of-Things applications, from net-enabled surveillance to mobile health.

Scaling of three-dimensional interconnect technology incorporating low temperature bonds to pitches of 10 µm for infrared focal plane array applications

This paper focuses on the application of low temperature bonding to the fabrication of three-dimensional (3D) massively parallel signal processors for high performance infrared imagers. We review two generations of the 3D heterogeneous integration process. The first generation process, compatible with pixel sizes in the 20 to 30 µm range, relies on low temperature epoxy bonding that is followed by the formation of copper-filled through-silicon vias (TSVs). The second generation process, scalable to pixel sizes of 10 µm and smaller, employs solid–liquid diffusion bonding of copper–tin to copper at 250 °C; the bonding follows TSV fabrication. To demonstrate the second generation process, we fabricated 3D test vehicles in the form of 640 × 512 arrays of vertical interconnects composed of TSVs and metal–metal bonds on a 10 µm pitch. We characterized electrical conductivity of the interconnects, the isolation resistance between the interconnects, and the operability and yield of the arrays. The successful demonstration of the interconnect technology paves the way to a functional demonstration of 3D signal processors in infrared imagers with 10 µm pixels.

Demonstration of low cost TSV fabrication in thick silicon wafers

Low cost wafer-level chip-scale vacuum packaging (WLCSVP) imposes unique constraints on potential implementation of through-silicon vias (TSVs). A WLCSVP requires a relatively thick substrate to prevent mechanical failure. Two approaches for integrating TSVs in thick silicon wafers have been successfully demonstrated. Both approaches enable TSV formation from the backside of a device wafer and are compatible with the requirements of subsequent packaging operations. We achieved low contact resistance between TSVs and frontside Ti/Cu and Al metallization, while demonstrating high isolation resistance and high TSV yield.

Highly integrated thermoelectric coolers

Thermoelectric coolers (TECs) are an effective technology for managing heat loads in high-performance electronic components. While most TECs are fabricated using bulk thermoelectric (TE) materials, thin-film thermoelectrics have been shown to be a viable alternative. Thin-film TE coolers (TFTECs) have several advantages in comparison with bulk devices, such as reduced form factor and improved heat pumping. However, the current TFTEC fabrication process does not take full advantage of the thin-film nature of the TE materials-the individual TE couples are fabricated as stand-alone subcomponents one die at a time. We report on a novel wafer-scale TFTEC fabrication process that is expected to improve the performance of TFTECs and enable their integration with other semiconductor devices. This highly integrated thermoelectric cooler (HITEC) approach is based on the same design methodology that is employed in silicon CMOS integrated circuits. By taking advantage of wafer-level processes, HITEC is scalable to larger device sizes and and higher manufacturing volumes. Furthermore, HITEC reduces the number of layers and interfaces in TFTECs, which minimizes thermal parasitic losses. Thus the HITEC approach enables improvements in TFTECs scalability, cost, and performance.

TSV-Last, Heterogeneous 3D Integration of a SiGe BiCMOS Beamformer and Patch Antenna for a W-Band Phased array Radar

We report a TSV-last, heterogeneous 3D integration process for millimeter wave solid state tiles for use in the demonstration of a W-band active electronically scanned array (AESA) radar system. Each phased array tile consists of a high speed SiGe BiCMOS beamformer chip, vertically integrated with an advanced, multi-metallization level glass substrate which includes an RF interposer and a patch antenna array. This paper will briefly describe the SiGe and glass circuit layers, along with the main components of the 3D integration processing and assembly. Electrical testing of the SiGe and glass chips was conducted at various points during the integration processing, including DC and RF measurements after the two chips were bonded together. Additionally, DC testing of TSV chains was completed along with thermal cycling. The results of this work indicated a successful initial prototype demonstration of 3D heterogeneous integrated phased array tiles, which can be used for a multi-tile subarray assembly and subsequent sensor system demonstration.