Christopher M. Schnabel

SiGe HBTs with cut-off frequency of 350 GHz

This work reports on SiGe HBTs with f/sub T/ of 350 GHz. This is the highest reported f/sub T/ for any Si-based transistor as well as any bipolar transistor. Associated f/sub max/ is 170 GHz, and BV/sub CEO/ and BV/sub CBO/ are measured to be 1.4 V and 5.0 V, respectively. Also achieved was the simultaneous optimization of f/sub T/ and f/sub max/ resulting in 270 GHz and 260 GHz, with BV/sub CEO/ and BV/sub CBO/ of 1.6 V and 5.5 V, respectively. The dependence of device performance on bias condition and device dimension has been investigated. Considerations regarding the extraction of such high f/sub T/ and f/sub max/ values are also discussed.

SiGe HBT technology with f/sub max//f/sub T/=350/300 GHz and gate delay below 3.3 ps

This work reports on SiGe HBT technology with f/sub max/ and f/sub T/ of 350 GHz and 300 GHz, respectively, and a gate delay below 3.3 ps. This is the highest reported speed for any Si-based transistor in terms of combined performance of f/sub max/ and f/sub T/ both of which exhibit 300 GHz and above. Associated BV/sub CEO/ and BV/sub CBO/ are measured to be 1.7 V and 5.6 V, respectively. The dependence of device performance on bias condition and device dimension has been investigated. Considerations regarding the extraction of such high f/sub max/ and f/sub T/ values are also discussed.

SiGe HBTs for millimeter-wave applications with simultaneously optimized f/sub T/ and f/sub max/ of 300 GHz

Millimeter-wave applications are gaining growing interest in recent times. To meet the challenges for such applications, SiGe HBTs, with simultaneously optimized f/sub T/ and f/sub max/ of >300 GHz, are developed. To the authors knowledge, this is the first report of f/sub T/ and f/sub max/ both exceeding 300 GHz for any Si-based transistor. BV/sub CEO/ and BV/sub CBO/ are 1.6 V and 5.5 V, respectively, with peak current gain of 660. Noise measurement shows F/sub min/ of 0.45 dB and 1.4 dB at 10 GHz and 25 GHz with associate gain of 14 dB and 8 dB, respectively. The results indicate SiGe HBTs are highly suitable for the rapidly expanding millimeter-wave applications.

Experimental Study of Gate-First FinFET Threshold-Voltage Mismatch

In this brief, threshold voltage mismatch of fully integrated n-type FinFETs based on a gate-first process was studied experimentally. Significantly improved threshold voltage mismatch due to undoped FIN body was confirmed with the experimental data. By comparing mismatch values of thin- and thick-oxide nMOS, we found that factors, which do not scale with gate oxide thickness, including line edge roughness and metal-gate granularity (MGG), can explain ~ 60% of total mismatch of thin-oxide devices. Moreover, we report a convex shape of threshold voltage mismatch following the increase of the number of FINs and propose a possible explanation of the abnormal behavior. Due to channel width quantization, two competing contributors impact mismatch: as FIN number becomes smaller mismatch due to MGG likely play an important role which increases threshold voltage mismatch, whereas FIN number becomes larger, systematic variation becomes the main factor, which also increases threshold voltage mismatch.

RF FET layout and modeling for design success in RFCMOS technologies

This paper presents challenges in creating high quality RF FET layouts and models in CMOS technologies spanning 0.25 /spl mu/m to 90 nm nodes. The focus is on developing a comprehensive methodology to provide robust, high performance parameterized RF FET layout cells and corresponding scalable RF models to enable RF designs that fully leverage the cost benefit potential of CMOS technology.