Chulho Chung

Five-Step (Pad–Pad Short–Pad Open–Short–Open) De-Embedding Method and Its Verification

We present the method for five-step (pad-pad short-pad open-short-open) on-chip parasitic de-embedding. Its validation is verified by gate electrode resistance and input capacitance of transistors based on 45 -nm CMOS process. Optimized dummy structures to remove the parasitic components due to the pad and routing metal are proposed. Parameters extracted by the proposed method have excellent physical and theoretical trends.

RF Model of BEOL Vertical Natural Capacitor (VNCAP) Fabricated by 45-nm RF CMOS Technology and Its Verification

A radio-frequency equivalent circuit model for the symmetric vertical natural capacitor (VNCAP) in a 45 nm low-standby-power CMOS process is presented. The average effective capacitance density of 2.24 fF/ mum2 is obtained from VNCAPs of 1 times (M1 - M5) + 2 times (M6 - M7) metal-layer configuration after the open-short de-embedding procedure. The proposed model consists of main series capacitance network and lossy substrate network. The accuracy of the VNCAP model is verified S-parameters, effective capacitance Ceff, and quality factor (Q) up to 15 GHz. The proposed model can accurately describe the frequency characteristics of S-parameters, Ceff, and Q-factor up to 15 GHz for VNCAPs with different widths and lengths.

Effects of Parasitic Capacitance, External Resistance, and Local Stress on the RF Performance of the Transistors Fabricated by Standard 65-nm CMOS Technologies

Effects of parasitic capacitance, external resistance, and local stress on the radio-frequency (RF) performance of the transistors fabricated by 65-nm CMOS technology have been investigated. The effect of parasitic capacitance, particularly Cgb, becomes significant due to the reduced spacing between the gate and the substrate contact (SC) in proportion to scaling down. Current drivability (Idsat) per unit width has been improved through introduction of mobility enhancement techniques. The influence of external resistance becomes more pronounced for large-dimensional RF transistors due to severe IR drop. Such improved current drivability and large external resistance is responsible for dc performance (gm) degradation and, eventually, cutoff frequency (fT) degradation. Local stress effects associated with silicon nitride capping layer and STI stress have been investigated. fT is largely affected by local stress change, i.e., gm degradation at minimal gate poly (GP) pitch and gate-to-active spacing, fT is dominated by increased parasitic capacitance (Cgb) with increasing GP pitch and gate-to-active spacing. Above 10% improvement in fT has been observed through layout optimization for Cgb reduction by increasing the transistor active-to-SC spacing.

A 5 GHz transformer-coupled shifting CMOS VCO using bias-level technique

We report a low phase noise transformer-coupled CMOS VCO using a bias-level shifting technique. Two fully integrated voltage-controlled oscillators (VCOs) are presented as a proof of concept. A conventional LC VCO with a current source achieves a phase noise of -116.67 dBc/Hz at 1 MHz offset from the 5.6 GHz center frequency, taking 3.9 mA from a 1.5 V power supply. The proposed transformer-coupled VCO achieves a phase noise of -124.17 dBc/Hz at 1 MHz offset from a 5.8 GHz carrier frequency with 5.1 mA bias current from 1.5 V power supply. The VCO performances are compared with previously reported CMOS VCOs in the range of 4-6 GHz oscillation frequencies.

Characterization and Modeling of RF-Performance

The fluctuation of RF performance (particularly for f_T: cutoff frequency) in the transistors fabricated by 90-nm CMOS technology has been investigated. The modeling for f_T fluctuation is well fitted with the measurement data within approximately 1% error. Low-V_t transistors (fabricated by lower doping concentration in the channel) show higher f_T fluctuation than normal transistors. Such a higher f_T fluctuation results from C_gg (total gate capacitance) variation rather than g_m variation. More detailed analysis shows that C_gs + C_gb (charges in the channel and the bulk) are predominant factors over C_gd (charges in LDD/halo region) to determine C_gg fluctuation.

(f_{T})

Cut-off frequency (f_T) of 300 GHz and 230 GHz for NMOS and PMOS is demonstrated for transistors with a gate length of 35 nm fabricated by 45 nm standard CMOS technology. Current gain (H₂₁) and noise (flicker and thermal) is improved with scaling down technology. Power gain (G_u) increase is slow down and even saturated at 45 nm as technology advances. Such saturation in power gain is attributed to rapid increase in g_ds (drain conductance). Additional efforts are required to reduce g_ds for continuous improvement in power gain with the scaling. V_th optimization can be one of options to achieve better g_ds.

Fluctuation in MOSFETs

We report a high performance NPN bipolar junction transistor (BJT) processed in standard CMOS process that is applied to realize the direct conversion GSM receiver and DVB-H tuner. Through the variation of the base doping profile, performance of the NPN BJT has been tailored to meet the requirements of the RF circuits. Careful optimization is performed using both simulation and experiment. Optimized NPN BJT has maximum current gain of ~44, collector-emitter breakdown voltage of ~7V, collector-base breakdown voltage of ~20V, early voltage of ~25V, cutoff frequency of ~8.0GHz, and maximum oscillation frequency of ~11.6GHz. Low frequency noise characteristics of the NPN BJTs are investigated and the best structure for low noise level is identified. The corner frequency of the 1/f noise is ~2kHz at a collector current of ~1.7mA, which is ~4 orders lower than that of NMOS. As the flicker noise level is much lower than the CMOS, NPN BJT is used to realize the zero intermediate frequency (ZIF) direct conversion receiver (DCR) for GSM transceiver and DVB-H tuner. The resulting GSM receiver chain has a gain of over 50dB and noise figure of 2.5-3.0dB. For DVB-H tuner operating in the range of 470-850MHz, NF of 4.5dB and IIP3 of -5dBm are achieved at a gain of 64dB