Hansu Oh

S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond

For the first time, S-RCAT (sphere-shaped-recess-channel-array transistor) technology has been successfully developed in a 2Gb density DRAM with 70nm feature size. It is a modified structure of the RCAT (recess-channel-array transistor) and shows an excellent scalability of recessed-channel structure to sub-50nm feature size. The S-RCAT demonstrated superior characteristics in DIBL, subthreshold swing (SW), body effect, junction leakage current and data retention time, comparing to the RCAT structure, in this paper, S-RCAT is proved to be the most promising DRAM array transistor suitable for sub-50nm and mobile applications.

The excellent scalability of the RCAT (recess-channel-array-transistor) technology for sub-70nm DRAM feature size and beyond

The technology innovation for extending the RCAT structure to the sub-70nm DRAM is presented. The new technology overcomes the problems induced by shrinkage of the RCAT structure and meets the requirements for the next generation DRAMs, such as high speed and low power performance. The technology roadmap down to the 50nm DRAM feature size of the RCAT development is presented.

Five-Step (Pad–Pad Short–Pad Open–Short–Open) De-Embedding Method and Its Verification

We present the method for five-step (pad-pad short-pad open-short-open) on-chip parasitic de-embedding. Its validation is verified by gate electrode resistance and input capacitance of transistors based on 45 -nm CMOS process. Optimized dummy structures to remove the parasitic components due to the pad and routing metal are proposed. Parameters extracted by the proposed method have excellent physical and theoretical trends.

RF Model of BEOL Vertical Natural Capacitor (VNCAP) Fabricated by 45-nm RF CMOS Technology and Its Verification

A radio-frequency equivalent circuit model for the symmetric vertical natural capacitor (VNCAP) in a 45 nm low-standby-power CMOS process is presented. The average effective capacitance density of 2.24 fF/ mum2 is obtained from VNCAPs of 1 times (M1 - M5) + 2 times (M6 - M7) metal-layer configuration after the open-short de-embedding procedure. The proposed model consists of main series capacitance network and lossy substrate network. The accuracy of the VNCAP model is verified S-parameters, effective capacitance Ceff, and quality factor (Q) up to 15 GHz. The proposed model can accurately describe the frequency characteristics of S-parameters, Ceff, and Q-factor up to 15 GHz for VNCAPs with different widths and lengths.

Effects of Parasitic Capacitance, External Resistance, and Local Stress on the RF Performance of the Transistors Fabricated by Standard 65-nm CMOS Technologies

Effects of parasitic capacitance, external resistance, and local stress on the radio-frequency (RF) performance of the transistors fabricated by 65-nm CMOS technology have been investigated. The effect of parasitic capacitance, particularly Cgb, becomes significant due to the reduced spacing between the gate and the substrate contact (SC) in proportion to scaling down. Current drivability (Idsat) per unit width has been improved through introduction of mobility enhancement techniques. The influence of external resistance becomes more pronounced for large-dimensional RF transistors due to severe IR drop. Such improved current drivability and large external resistance is responsible for dc performance (gm) degradation and, eventually, cutoff frequency (fT) degradation. Local stress effects associated with silicon nitride capping layer and STI stress have been investigated. fT is largely affected by local stress change, i.e., gm degradation at minimal gate poly (GP) pitch and gate-to-active spacing, fT is dominated by increased parasitic capacitance (Cgb) with increasing GP pitch and gate-to-active spacing. Above 10% improvement in fT has been observed through layout optimization for Cgb reduction by increasing the transistor active-to-SC spacing.

A 5 GHz transformer-coupled shifting CMOS VCO using bias-level technique

We report a low phase noise transformer-coupled CMOS VCO using a bias-level shifting technique. Two fully integrated voltage-controlled oscillators (VCOs) are presented as a proof of concept. A conventional LC VCO with a current source achieves a phase noise of -116.67 dBc/Hz at 1 MHz offset from the 5.6 GHz center frequency, taking 3.9 mA from a 1.5 V power supply. The proposed transformer-coupled VCO achieves a phase noise of -124.17 dBc/Hz at 1 MHz offset from a 5.8 GHz carrier frequency with 5.1 mA bias current from 1.5 V power supply. The VCO performances are compared with previously reported CMOS VCOs in the range of 4-6 GHz oscillation frequencies.

Characterization and Modeling of RF-Performance

The fluctuation of RF performance (particularly for f_T: cutoff frequency) in the transistors fabricated by 90-nm CMOS technology has been investigated. The modeling for f_T fluctuation is well fitted with the measurement data within approximately 1% error. Low-V_t transistors (fabricated by lower doping concentration in the channel) show higher f_T fluctuation than normal transistors. Such a higher f_T fluctuation results from C_gg (total gate capacitance) variation rather than g_m variation. More detailed analysis shows that C_gs + C_gb (charges in the channel and the bulk) are predominant factors over C_gd (charges in LDD/halo region) to determine C_gg fluctuation.

(f_{T})

For the first time, novel robust capacitor (Leaning exterminated Ring type Insulator - LERI) and new storage node (SN) contact process (Top Spacer Contact - TSC) are successfully developed with 82nm feature size. These novel processes drastically improved electrical characteristics such as cell capacitance, parasitic bit line capacitance and cell contact resistance, compared to a conventional process. The most pronounced effect using the LERI in COB structure is to greatly improve cell capacitance without twin bit failure. In addition, the TSC technology has an ability to remove a critical ArF lithography. By using the LERI and TSC processes in 82nm 512M DDR DRAM, the cell capacitance of 32fF/cell is achieved with Toxeq of 2.3nm and the parasitic bit line capacitance is reduced by 20%, resulted in great improvement of tRCD (1.5ns).

Fluctuation in MOSFETs

Cut-off frequency (f_T) of 300 GHz and 230 GHz for NMOS and PMOS is demonstrated for transistors with a gate length of 35 nm fabricated by 45 nm standard CMOS technology. Current gain (H₂₁) and noise (flicker and thermal) is improved with scaling down technology. Power gain (G_u) increase is slow down and even saturated at 45 nm as technology advances. Such saturation in power gain is attributed to rapid increase in g_ds (drain conductance). Additional efforts are required to reduce g_ds for continuous improvement in power gain with the scaling. V_th optimization can be one of options to achieve better g_ds.

Novel robust cell capacitor (Leaning Exterminated Ring type Insulator) and new storage node contact (Top Spacer Contract) for 70nm DRAM technology and beyond

Novel high-k MIM capacitor technology for mixed-signal/RF applications has been successfully developed by introducing multilayered high-k dielectric(Ta/sub 2/O/sub 5//HfO/sub 2//Ta/sub 2/O/sub 5/) and NH/sub 3/ plasma electrode-dielectric interfaces treatments. For the first time, we have simultaneously achieved high capacitance of 4fF/um/sup 2/ and low leakage current of 100nA/cm/sup 2/ at high temperature of 125/spl deg/C with ultra low VCC(a=16.9ppm/V/sup 2/, b=5.2ppm/V) and high Q(/spl sim/107 at 2.4GHz and 5.4pF).