Chun-Hsing Li

A 0.6-V 0.33-mW 5.5-GHz Receiver Front-End Using Resonator Coupling Technique

In this study, a low-power and low-voltage 5.5-GHz receiver front-end circuit is designed using a resonator coupling technique. An on-chip transformer combined with the parasitic capacitances from a low-noise amplifier (LNA), a mixer, and the transformer itself comprises two coupled resonators of the resonator coupling network (RCN). The RCN functions as a balun, and couples energy from the LNA to the mixer. Under the critical coupling condition, the RCN gives a maximal current gain at resonance frequencies, equivalent to the same level by an ideal transformer. The analysis shows that the current gain is quite tolerable to the coupling coefficient variation, an advantageous feature for on-chip transformer design. The technique is verified by the receiver front-end in 0.18-μm CMOS technology. The RCN possess a current gain as high as 12 dB at 5.5 GHz. The measured input return loss, conversion gain, and third-order intermodulation intercept point of the entire circuit are 16 dB, 17.4 dB, and -1.5 dBm, respectively. The noise figure is 7.8 dB at the IF frequency of 1 MHz. The power consumption is only 0.33 mW from a 0.6-V supply. The required local oscillator power is only -9.5 dBm. This receiver front-end successfully demonstrates the resonator coupling technique.

A 1.2-V 5.2-mW 20–30-GHz Wideband Receiver Front-End in 0.18-

This paper presents a low-power wideband receiver front-end design using a resonator coupling technique. Inductively coupled resonators, composed of an on-chip transformer and parasitic capacitances from a low-noise amplifier, a mixer, and the transformer itself, not only provide wideband signal transfer, but also realize wideband high-to-low impedance transformation. The coupled resonators also function as a wideband balun to give single-to-differential conversion. Analytic expressions for the coupled resonators with asymmetric loads are presented for design guidelines. The proposed receiver front-end only needs a few passive components so that gain degradation caused by the passive loss is minimized. Hence, power consumption and chip area can be greatly reduced. The chip is implemented in 0.18-μm CMOS technology. The experimental result shows that the - 3-dB bandwidth can span from 20 to 30 GHz with a peak conversion gain of 18.7 dB. The measured input return loss and third-order intercept point are better than 16.7 dB and -7.6 dBm, respectively, over the bandwidth. The minimum noise figure is 7.1 dB. The power consumption is only 5.2 mW from a 1.2-V supply. The chip area is only 0.18 mm2 .

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This work presents a 147 GHz D-band fully differential amplifier design in 65 nm CMOS. By using a T-network, composed of three inductors, to replace an on-chip transformer, the proposed impedance transformation network can provide an impedance transformation ratio larger than one. So the passive gain can be acquired to increase the amplifier gain. The measured results show that the amplifier can provide power gain of 7.1 dB at 147 GHz. The power consumption is 104 mW from a 2 V supply voltage.

CMOS

An interconnecting technology using a Au-Au thermocompressive bond has been successfully developed for microelectromechanical system (MEMS) heterogeneous chip integration in this paper. The Daisy chain and RF transition structures are both designed and fabricated for the electrical characterization of the interconnect scheme. Measured dc contact resistance is about 14 ±5 m¿ for the bonding interface of Ni (1 ¿m)/Au (0.4 ¿m)/Au (0.4 ¿m)/Ni (1 ¿m) with a pad size of 40 ¿m in diameter. The electrical transition between two chips, which have coplanar waveguides (CPWs) and microstrip lines, respectively, can be well interconnected with less than - 15 dB return loss and - 1.8 dB insertion loss up to 50 GHz without implementing complex structure designs and extra impedance matching networks in the transition by employing this technology. Meanwhile, it is found that the mechanical strength for the interconnecting bond can be as large as 100 MPa. A low-power RF low-noise amplifier has been successfully designed, fabricated, and utilized in this paper to demonstrate the feasibility of the interconnecting technology for RF MEMS heterogeneous chip integration by integrating a Taiwan Semiconductor Manufacturing Corporation 0.18-¿m RF complimentary metal-oxide-semiconductor chip with a silicon carrier, where high Q MEMS inductors are fabricated and utilized for good circuit performance in terms of excellent impedance matching, power gain, and gain flatness.

A 147 GHz fully differential D-band amplifier design in 65 nm CMOS

A low-power and high-performance 340-GHz heterodyne receiver front end (RFE) optimized for terahertz (THz) biomedical imaging applications is proposed in this paper. The THz RFE consists of an on-chip patch antenna, a single-balanced mixer, and a triple-push harmonic oscillator. The oscillator adopts a proposed harmonic oscillator architecture which can provide differential output by extracting output signals from the same current loop without any additional balun required. The mixer biased in the subthreshold region is designed not only to have high conversion gain and low noise figure by choosing the output intermediate frequency well above the flicker-noise corner frequency, but the required local oscillator (LO) power can also be as low as -11 dBm. Such a low demand on the LO power makes the proposed mixer very suitable for THz applications in which the achievable LO power is very limited. The impact of unavoidable slots for passing design rule checks on the performance of an on-chip patch antenna is also presented. The proposed THz RFE is implemented in a 40-nm digital complementary metal-oxide-semiconductor technology. The measured voltage conversion gain is -1.7 dB at 335.8 GHz, while the mixer and the oscillator only consume 0.3 and 52.8 mW, respectively, from a 1.1 V supply. The proposed THz RFE is employed to set up a THz transmissive imaging system which can provide spatial resolution of 1.4 mm.

An Interconnecting Technology for RF MEMS Heterogeneous Chip Integration

This paper presents a THz imaging system composed of a signal source and a signal sensor in CMOS technology. The signal source integrates a 338 GHz oscillator in 40-nm CMOS and an antenna array on a Benzocyclobutene (BCB) carrier using the SoP (System-on-Package) technique. The measured EIRP achieves +8 dBm. The signal sensor is implemented in 0.18 μm CMOS. The measured maximum responsivity is 632 kV/W at 332 GHz. The signal source and signal sensor consume dc power of 37.5 mW and 7.92 mW, respectively. The resolution of the proposed THz imaging system is 4 mm.

A 340-GHz Heterodyne Receiver Front End in 40-nm CMOS for THz Biomedical Imaging Applications

A low-power triple-push oscillator with differential output is proposed in this letter. By extracting signals from the same current loop, the oscillator can naturally provide differential output without any additional active circuit or passive balun required. Therefore, the output power can be increased and the chip area and power consumption can be reduced. Realized in 40 nm CMOS technology, the proposed oscillator can oscillate at 340.6 GHz while providing equivalent isotropically radiated power (EIRP) as -21.8 dBm. The power consumption is only 34.1 mW from a 0.9 V supply. The oscillator core only occupies area of 0.028 mm2.

CMOS THz transmissive imaging system

A broadband interconnect for THz heterogeneous system integration is proposed using a resonator coupling technique. Two resonators, deployed on a chip and a carrier, respectively, are coupled through the electromagnetic field to provide a low-loss interconnect in a broadband manner. Simulation results indicate an insertion loss of 0.32 dB at 170 GHz while covering 3-dB bandwidth from 100 to 344 GHz. Measurement can be conducted to verify its performance only from 140 GHz to 220 GHz, due to equipment limit. The measured minimum insertion loss is 0.47 dB at 164 GHz.

A 340 GHz Triple-Push Oscillator With Differential Output in 40 nm CMOS

A flip-chip interconnect is proposed to achieve good electrical performance applicable to millimeter-wave applications. By Au-Au thermocompression technique, the transition structure provides continuity of characteristic impedance from the on-carrier CPW line to the on-chip microstrip line, as well as smooth current flow. Parameter optimization further indicates that the tapered reference ground connection is insensitive to the frequency response. Characterization of the structure is conducted by the thur-reflect-line (TRL) calibration technique to test the flip-chip interconnects up to 50 GHz. Measurement results show that return loss is better than 15 dB and insertion loss smaller than 1.7dB up to 50 GHz. The broadband transition structure is suitable for high frequency application without any external matching network.

A broadband interconnect for THz heterogeneous system integration

A low-cost broadband bondwire interconnect is proposed for THz heterogeneous system integration. A transversal path composed of two transmission lines and a bondwire is introduced to effectively reduce the bondwire effect of an original signal path consisted of a single bondwire only. Simulation results indicate that the return loss and insertion loss can be better than 15 dB and 2.3 dB from dc to 456 GHz, respectively. Measured interconnect loss is around 0 dB to 1.5 dB from 320 to 340 GHz.