Chien-Nan Kuo

A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13

A fully integrated direct-conversion tuner is implemented in 0.13 mum CMOS technology. A broadband noise-canceling balun LNA with the proposed dual cross-coupling technique helps achieve an overall receiver noise figure from 3.7 to 4.3 dB while consuming only 3.6 mW. The proposed current-mode switching scheme improves the achievable SNIR with a gain step of 15 dB, providing IIP3 improvement of 18 dB and NF degradation of only 6 dB. Moreover, design trade-offs are carefully considered in designing the baseband circuit, which provides wide gain tuning and bandwidth accuracy with a DC offset residual less than 6 mV. The measured maximum SNR values are better than 30 dB over wide input power levels, ensuring robust reception in a mobile environment. All circuit blocks are operated at 1.2 V. As a result, the tuner consumes power as low as 114 mW in the continuous mode. This compact tuner supports both UHF and L- bands, and occupies only 7.2 mm2 die area.

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A CMOS low noise amplifier (LNA) is designed with output tunable over an ultra-wideband. A cascode configuration is employed in the circuit, with inductive source degeneration (ISD) and a three-section bandpass Chebyshev filter to achieve broadband input impedance matching. A source follower acts as the buffer stage for broadband output impedance matching. Signal output is band-tunable over the frequency range from 6 GHz to 10 GHz. The circuit is fabricated in a standard 0.18 /spl mu/m CMOS process. Circuit performance achieves maximum power gain, S21, of 11.6 dB, the input return loss, S11, better than 9 dB, and the best noise figure of 4.2 dB. The circuit consumes power of 11.6 mW.

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A CMOS reconfigurable LNA is reported. By combination of switched inductors and varactors it performs continuous frequency tuning from 2.4 to 5.4 GHz with 500 MHz 3 dB-bandwidth. Switching transistor is used to provide variable gain control over a 12 dB-range. The LNA supports standards including Bluetooth, WiMAX, UWB mode-1, 802.11 b/g and part of 802.11a. Fabricated in 0.13 um CMOS process the LNA achieves up to 25 dB power gain, 2.2 dB noise figure, -1 dBm IIP3 while consuming less than 5 mW from 1-V power supply.

A 6-10-GHz ultra-wideband tunable LNA

A new low-power CMOS active balun is designed for ultra-wideband applications, using a pair of common-source NMOS and common-gate PMOS transistors. This balun gives an impedance transformation ratio of 1:2. Without compensation feedback, the circuit provides a differential signal within 2dB and 3deg of gain and phase imbalance, respectively, up to 8-GHz. Total power consumption is only 1.44 mW at the supply voltage of Vdd=1.2V, much less than 12 mW of the traditional active balun. This saves 88% of power. The circuit can be fully integrated in RFIC for low power and low cost

A 2.4 to 5.4 GHz Low Power CMOS Reconfigurable LNA for Multistandard Wireless Receiver

This paper presents a low-power wideband receiver front-end design using a resonator coupling technique. Inductively coupled resonators, composed of an on-chip transformer and parasitic capacitances from a low-noise amplifier, a mixer, and the transformer itself, not only provide wideband signal transfer, but also realize wideband high-to-low impedance transformation. The coupled resonators also function as a wideband balun to give single-to-differential conversion. Analytic expressions for the coupled resonators with asymmetric loads are presented for design guidelines. The proposed receiver front-end only needs a few passive components so that gain degradation caused by the passive loss is minimized. Hence, power consumption and chip area can be greatly reduced. The chip is implemented in 0.18-μm CMOS technology. The experimental result shows that the - 3-dB bandwidth can span from 20 to 30 GHz with a peak conversion gain of 18.7 dB. The measured input return loss and third-order intercept point are better than 16.7 dB and -7.6 dBm, respectively, over the bandwidth. The minimum noise figure is 7.1 dB. The power consumption is only 5.2 mW from a 1.2-V supply. The chip area is only 0.18 mm2 .

Low power 8-GHz ultra-wideband active balun

In this paper, a direct up-conversion mixer with wide intermediate frequency (IF) bandwidth is designed and fabricated for 60-GHz applications. The up-converted differential signal is transformed to single-ended signal through an on-chip balun. In addition, an injection-locked frequency tripler is integrated for local oscillator signal generation. The measured results shows the maximum conversion gain of -5.6 dB, the input-referred 1-dB compression point (IP1dB) of -14 dBm, the third-order intercept point (IIP3) of -4 dBm, and 3-dB IF bandwidth of 3.5 GHz. The proposed up-conversion mixer is fabricated using 0.13-μm standard CMOS technology, and it draws only 2.25 mA from 1.2-V supply.

A 1.2-V 5.2-mW 20–30-GHz Wideband Receiver Front-End in 0.18-

This work presents a 147 GHz D-band fully differential amplifier design in 65 nm CMOS. By using a T-network, composed of three inductors, to replace an on-chip transformer, the proposed impedance transformation network can provide an impedance transformation ratio larger than one. So the passive gain can be acquired to increase the amplifier gain. The measured results show that the amplifier can provide power gain of 7.1 dB at 147 GHz. The power consumption is 104 mW from a 2 V supply voltage.

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The design of millimeter-wave frequency triplers using sub-harmonic mixing and injection-locking is discussed. The design goals are aimed at low power consumption, high harmonic rejection, and bandwidth extension. Several circuit design techniques will be reviewed for consideration of these goals. These frequency triplers are all designed and implemented in CMOS technology.

CMOS

A 5 GHz, 30-dBm CMOS T/R switch implemented in 90 nm CMOS is reported. A body isolation technique is employed and optimized for power handling capability. Inductors are employed with the transistor switches for parallel resonance to improve isolation. Thick oxide NMOS transistors are used for the switching transistors and placed inside the inductors to reduce the active chip area to approximately 0.2 mm2. 0.9-dB insertion loss for both TX and RX modes is achieved with a 5-V control voltage.

A CMOS Up-Conversion Mixer with Wide IF Bandwidth for 60-GHz Applications

This paper presents the on-chip transmission line modeling and applications to circuit design at millimeter-wave (ram-wave) frequencies. The microstrip model of circuit simulators benefits in fast calculations of the characteristics of microstrip lines. As the structure of on-chip microstrip differs from the modeled structure, two key parameters of the microstrip model need to be modified for the different electromagnetic (EM) behavior according to the measured microstrip line. With proper parameters, the traditional transmission line model is able to accurately predict the real characteristic of on-chip microstrip lines without time-consuming EM simulation. A mm-wave microstrip line filter and a single-stage cascode low noise amplifier (LNA) are fabricated to verify the model. All passive components for input/output matching networks and bias networks are on-chip. The LNA takes the supply voltage and dc current of 1.4 V and 10 mA, respectively. A gain of 3.8 dB and an input/output return loss of 8.5/7.0 dB are measured at 60.3 GHz. The simulation results in both circuits are in good agreement with measured data.