Ming-Ching Kuo

Wideband LNA Compatible for Differential and Single-Ended Inputs

This letter presents a wideband low-noise amplifier (LNA) that supports both differential and single-ended inputs, while providing differential output. The LNA is implemented in 0.13 mum CMOS technology. For sub-1 GHz wideband applications, this LNA achieves 22.5 dB voltage gain, +1 dBm IIP3, and 2.5 dB NF in the differential receiving mode, while achieving 23 dB voltage gain, -0.5 dBm IIP3, and 2.65 dB NF in the single-ended receiving mode. The LNA core circuit draws 2.5 mA from 1.2 V supply voltage, and occupies a small chip area of 0.06 mm2.

A 1.2-V 5.2-mW 20–30-GHz Wideband Receiver Front-End in 0.18-

This paper presents a low-power wideband receiver front-end design using a resonator coupling technique. Inductively coupled resonators, composed of an on-chip transformer and parasitic capacitances from a low-noise amplifier, a mixer, and the transformer itself, not only provide wideband signal transfer, but also realize wideband high-to-low impedance transformation. The coupled resonators also function as a wideband balun to give single-to-differential conversion. Analytic expressions for the coupled resonators with asymmetric loads are presented for design guidelines. The proposed receiver front-end only needs a few passive components so that gain degradation caused by the passive loss is minimized. Hence, power consumption and chip area can be greatly reduced. The chip is implemented in 0.18-μm CMOS technology. The experimental result shows that the - 3-dB bandwidth can span from 20 to 30 GHz with a peak conversion gain of 18.7 dB. The measured input return loss and third-order intercept point are better than 16.7 dB and -7.6 dBm, respectively, over the bandwidth. The minimum noise figure is 7.1 dB. The power consumption is only 5.2 mW from a 1.2-V supply. The chip area is only 0.18 mm2 .

\mu{\hbox {m}}

A low-power and high-performance 340-GHz heterodyne receiver front end (RFE) optimized for terahertz (THz) biomedical imaging applications is proposed in this paper. The THz RFE consists of an on-chip patch antenna, a single-balanced mixer, and a triple-push harmonic oscillator. The oscillator adopts a proposed harmonic oscillator architecture which can provide differential output by extracting output signals from the same current loop without any additional balun required. The mixer biased in the subthreshold region is designed not only to have high conversion gain and low noise figure by choosing the output intermediate frequency well above the flicker-noise corner frequency, but the required local oscillator (LO) power can also be as low as -11 dBm. Such a low demand on the LO power makes the proposed mixer very suitable for THz applications in which the achievable LO power is very limited. The impact of unavoidable slots for passing design rule checks on the performance of an on-chip patch antenna is also presented. The proposed THz RFE is implemented in a 40-nm digital complementary metal-oxide-semiconductor technology. The measured voltage conversion gain is -1.7 dB at 335.8 GHz, while the mixer and the oscillator only consume 0.3 and 52.8 mW, respectively, from a 1.1 V supply. The proposed THz RFE is employed to set up a THz transmissive imaging system which can provide spatial resolution of 1.4 mm.

CMOS

A low-power triple-push oscillator with differential output is proposed in this letter. By extracting signals from the same current loop, the oscillator can naturally provide differential output without any additional active circuit or passive balun required. Therefore, the output power can be increased and the chip area and power consumption can be reduced. Realized in 40 nm CMOS technology, the proposed oscillator can oscillate at 340.6 GHz while providing equivalent isotropically radiated power (EIRP) as -21.8 dBm. The power consumption is only 34.1 mW from a 0.9 V supply. The oscillator core only occupies area of 0.028 mm2.

A 340-GHz Heterodyne Receiver Front End in 40-nm CMOS for THz Biomedical Imaging Applications

A dual-mode, triband RF front-end receiver for GSM-900, DCS-1800 and IEEE 802.11b/g is introduced. With advanced architecture selection and frequency plan, only a single VCO and frequency synthesizer are required for both GSM/GPRS cellular and IEEE 802.11b/g WLAN. The receiver front-end has been realized in a 0.25 /spl mu/m CMOS process. It dissipates about 30 mA from a 2.7 V supply for all modes and exhibits noise figures of 3 dB for the GSM-900 band, 5.9 dB for the DCS-1800 band, and 5.7 dB for 2.4 GHz WLAN.

A 340 GHz Triple-Push Oscillator With Differential Output in 40 nm CMOS

A broadband interconnect for THz heterogeneous system integration is proposed using a resonator coupling technique. Two resonators, deployed on a chip and a carrier, respectively, are coupled through the electromagnetic field to provide a low-loss interconnect in a broadband manner. Simulation results indicate an insertion loss of 0.32 dB at 170 GHz while covering 3-dB bandwidth from 100 to 344 GHz. Measurement can be conducted to verify its performance only from 140 GHz to 220 GHz, due to equipment limit. The measured minimum insertion loss is 0.47 dB at 164 GHz.

A CMOS WLAN/GPRS dual-mode RF front-end receiver

A low-cost broadband bondwire interconnect is proposed for THz heterogeneous system integration. A transversal path composed of two transmission lines and a bondwire is introduced to effectively reduce the bondwire effect of an original signal path consisted of a single bondwire only. Simulation results indicate that the return loss and insertion loss can be better than 15 dB and 2.3 dB from dc to 456 GHz, respectively. Measured interconnect loss is around 0 dB to 1.5 dB from 320 to 340 GHz.

A broadband interconnect for THz heterogeneous system integration

A dual-mode, triple-band RF front-end receiver for GSM900, DCS1800 and WCDMA is presented. Because the system concepts of GSM and WCDMA are totally different from the standards, the chip uses low-IF and zero-IF receiver architecture for GSM and WCDMA, respectively. This chip consists of three parallel LNAs and down-conversion mixers with on-chip LO I/Q generations. The receiver front-end has been implemented in a standard 0.25/spl mu/m CMOS process and consumes about 30-mA from a 2.7-V power supply for all modes. The measured double-side band noise figure and voltage gain are 3dB, 36dB for the GSM900, 5.9dB, 31dB for the DCS1800, and ?-dB, 17.2dB for the WCDMA, respectively.

A low-cost broadband bondwire interconnect for THz heterogeneous system integration

A dual-mode, triple-band RF front-end receiver for GSM900, DCS1800 and WCDMA is presented. Because the system concepts of GSM and WCDMA are totally different from the standards, the chip uses low-IF and zero-IF receiver architecture for GSM and WCDMA, respectively. This chip consists of three parallel LNAs and down-conversion mixers with on-chip LO I/Q generations. The receiver front-end has been implemented in a standard 0.25/spl mu/m CMOS process and consumes about 30-mA from a 2.7-V power supply for all modes. The measured double-side band noise figure and voltage gain are 3dB, 36dB for the GSM900, 5.9dB, 31dB for the DCS1800, and ?-dB, 17.2dB for the WCDMA, respectively.

A CMOS dual-mode RF front-end receiver for GSM and WCDMA

This letter presents a new tool of constant loss contours for matching network loss evaluation. With a certain source impedance, the contours illustrate the matching loss while an arbitrary load impedance is matched to the source impedance. The contours are also applied to millimeter-wave circuit design to help designers consider the circuit topologies, transistor sizes, and layout effects. A millimeter-wave CMOS low-noise amplifier has been optimized by using the constant loss contours. The measured results show a low noise figure of 4.85 dB and a gain of 21.0 dB at 79.5 GHz while only consuming 8 mW from a 1.0 V supply.