Chunfei Ye

High-speed differential IO crosstalk — The impact of phase, bit rate, jitter and equalization

Loss, reflection, and crosstalk are among the key factors in the design of high-speed differential channels for signal integrity. Some signal integrity techniques are used to improve link performance to compensate for loss, such as TXLE and receiver equalization using CTLE and DFE. When these techniques are used they also impact crosstalk. In this paper, impacts on crosstalk are studied for various factors including phase difference among aggressors and victim, jitter, and bit rate. TXLE of aggressors are studied in detail with several cases. Receiver equalization using CTLE and DFE is included to reveal how RX equalization responds to the crosstalk from aggressors. Observations are made through this study to guide future signal integrity simulation and design to properly control the crosstalk.

Improve signal integrity performance by using hybrid PCB stackup

FR4 is a commonly used material in industry to build printed circuit boards. However signals propagating in this media have significant attenuation when date rate gets higher and higher, gating the solution space. Low loss materials can be considered to enable longer board routing but they are very costly for most of commercial platforms. In this paper, hybrid PCB stackup is investigated. The investigation focuses on full channel signal integrity analysis. Simulations for SATA3 and PCIE3 show noticeable improvement of using this hybrid stackup. Such a hybrid is normally less costly than all low loss PCB stackup, thus achieving a good compromising between cost and performance for PCB design and manufacturing.

Via pattern design and optimization for differential signaling 25Gbps and above

Ground via design rules may need to be re-visited to support high-speed signaling for 25Gbps and above, according to our experience. In this paper, the study begins with some basic via patterns with different ground via placement to investigate loss, crosstalk, common mode, and electromagnetic field distribution to help understand the underlying physics. The benefit of joint anti-pad is also analyzed for signaling at 25Gbps and above. Impact of adjacent vias to the modeled via pair of interest is studied and it is found that the adjacent vias should be properly terminated and included in the modeling. Finally crosstalk study is performed for the given via patterns.

Interconnect impedance optimization for high speed IO up to 12Gbps under HVM condition

Differential impedance optimization is critical for high-speed IO design and has attracted lot of interests for decades. This paper focuses on impedance optimization on a general purpose server design for 10Gbps and above and use SAS3 (Serial Attached SCSI Gen3) as example under HVM (high volume manufacturing) condition. The study starts with theoretical analysis on a two-port network of three cascaded transmission lines to prove that there is an optimal characteristic impedance value of the middle section which can bring the lowest reflection and best transmission to the entire two-port network. In the SAS3 impedance optimization study, statistical distribution for each design variable is considered to address the HVM consideration. The result clearly shows that lower the impedance of baseboard and backplane yields better eye opening at the receiver for the given impedance design range from 85Ω to 100Ω. In other words, 85Ω design on baseboard and backplane is better in performance than 100Ω even if cables, connectors and SAS3 hard disk drives (HDDs) are designed at 100Ω per SAS3 specification.

Signal integrity performance degradation due to temperature variation in systems with re-drivers

Re-drivers are widely used in extending the solution space in high speed applications. However, recent lab data shows that the ambient temperature variation can lead to ~40mV degradation of the eye height at the receiver side on single re-driver system. In this paper, the authors will share key learnings of thermal impact on systems with both single re-driver and cascaded re-drivers. From these cases, the eye height is greatly reduced when temperature increases. This variation is due to resistance shifting of the output buffer, while most re-driver models do not account for it. An effective approach is applied to fine tune the equalization settings in the cascaded re-driver system. The learnings, together with the proposed approach, can help designers to design a robust, high performance, and cost-effective high speed link with re-drivers such as SAS-3, SATA-3, PCIe and USB, etc.

Package design challenges and optimizations in density efficient (Intel® Xeon® processor D) SoC

Xeon®-D[1] brings the high performance of Xeon® processors into a dense, low-power System-on-Chip (SoC). This paper addresses the importance of cost-performance trade off optimization for the Xeon®-D package. It describes how to determine the low cost package factors (size, footprint, pin map and layer count) without compromising the performance of the system. 10GbE signal integrity design and HSD pin map optimization are discussed. Low power architecture and package power delivery features including FIVR are presented in the paper as well.

Signaling enabler in high-speed system design by using hybrid stackup printed circuit board

FR4 is a commonly used material in industry to build printed circuit boards. However signals propagating in this media have significant attenuation when the frequency is going higher and higher. In this paper, hybrid PCB stack-up is studied for signal integrity design, where only specific layers of the board use low loss dielectric while the others are fabricated with traditional FR4 in order to have optimized cost-performance. The investigation focuses on full channel signal integrity analysis based on the proposed hybrid stackup. Simulations for Intel® Quick Path Interconnect (Intel® QPI) show noticeable improvement. Such a hybrid stackup is normally less costly than all low loss PCB stackup, thus achieving a good compromising between cost and performance for system design and production.

Signal integrity design of via with extra routing stub for device routing flexibility

Computer systems today show a trend toward higher data rate, smaller form factor and flexible routing option to accommodate different configurations. This paper presents signal integrity impact study of having a routing stub on via in order to have a choice of which device to use. Via with routing stub is modeled using 3-D field solver. Signal integrity analysis is performed for PCIE Gen3 (8Gbps) and SATA3 (6Gbps) to demonstrate the margin loss due to various routing stub lengths. For the simulated topology, results show that for routing stub longer than 100mils, there is significant margin loss, which may even result in no solution space for PCIE Gen3 and SATA3. For routing stub less than 50mils, there is a few inches of solution space reduction equivalently according to the data rate.