Chung-Hsien Hsu

SoC-level risk assessment using FMEA approach in system design with SystemC

As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting more attention in the design industry due to the rapid increasing rate of radiation-induced soft errors while the SoC fabrication enters the very deep submicron technology. Therefore, the SoC dependability becomes a critical issue in safety-critical applications. Validating such systems is imperative to guarantee the dependability of the systems before they are being put to use. Moreover, it is beneficial to assess the SoC robustness in early design phase in order to significantly reduce the cost and time of re-design. To fill such needs, in this study, we propose a useful IP-based SoC-level risk model using failure mode and effects analysis (FMEA) method to assess the robustness of a SoC in SystemC transaction-level modeling (TLM) design level. The proposed risk model is able to facilitate the measure of the robustness and scales of failure-induced risks in a system, which can be used to identify the critical components and major failure modes for protection so as to effectively reduce the impact of failures to the system. A case study is used to demonstrate our risk model under CoWare Platform Architect environment. A system verification tool was created to assist us in measuring the robustness of the system, in locating the weaknesses of the system, and in understanding the effect of faults on system failure behavior during the SoC design phase. The contribution of this work is to promote the dependability verification to TLM abstraction level that can significantly enhance the simulation performance, and provide the comprehensive results to validate the system dependability in early design phase for safety-critical applications.

System-Bus Fault Injection Framework in SystemC Design Platform

As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting more attention in the design industry while the SoC fabrication enters the very deep submicron technology. In this study, we present a new approach of system-bus fault injection in SystemC design platform, which can be used to assist us in performing the FMEA procedure during the SoC design phase. We demonstrate the feasibility of the proposed fault injection mechanism with an experimental ARM-based system.

A voltage-mode boost DC-DC converter with a constant-duty-cycle pulse control

The conventional voltage-mode hysteretic buck converters have the merit of fast response and yet stable operation. However, such merits cannot be extended to its counterpart boost converters. This is so simply because the waveforms of the input current and output voltage of buck version are in-phase, but they are out-of-phase in the boost version. Due to the design simplicity, this study presents a voltage-mode boost converter design. With the simple structure, the proposed converter achieves a good power efficiency, ranged from 85% to 93.52% for the load currents from 50mA to 300mA, and fast transient response, 6 μs for the load currents which are switched from 100 mA to 300 mA and from 300 mA to 100 mA.

On the implemenation of CAN buses to battery management systems

Controller Area Network (CAN) bus has been popularly employed in most of vehicles and it will be heavily involved to the electric vehicle (EV) applications. This paper presents a CAN-bus-based battery management system (BMS). The system allows the EV system to detect whether the battery is overloaded through the CAN nodes and disable non-safety-critical devices when the battery is overloaded to protect the battery and to prolong the life of battery.

Design of ultra-wide-load, high-efficient DC-DC buck converters

The paper presents the design of a current-mode control DC-DC buck converter with pulse-width modulation (PWM) mode. The converter achieves a current load ranged from 50 mA to 500 mA over 90% efficiency, and the maximum power efficiency is 95.6%, where the circuit was simulated with the TSMC 0.35 um CMOS process. In order to achieve ultra-wide-load high efficiency, this paper implements with two PMOS transistors as switches. Results show that the converter achieves above 90% efficiency at the range from 30 mA to 1200 mA with a maximum efficiency of 96.36%. Results show that, with the additional switch transistor, the current load range is expanded more than double. With two PMOS transistors, the proposed converter can also achieve 3 different load ranges so that it can be programmed for the applications which are operated at those three different load ranges.

Lithium battery models for battery charging and system loading

The paper presents the circuit model for both battery charging and system loading (or battery discharging) of Lithium batteries. The model parameters can be derived from the given data sheet of a battery manufacturer. Results show that, at the battery discharging and system loading conditions, the errors between the measurement results and the simulated results are 1.6% and 0.548% for system loading and battery charging, respectively. Thus, the proposed circuit model provides sufficient accuracy for battery simulation and fault diagnosis.

A single-inductor programmable-output (SIPO) DC-DC converter for low power applications

This paper presents the first-ever single-inductor programmable-output (SIPO) DC-DC Converters. A SIPO converter is comprised of a DC-DC converter and a Phase-locked Loop (PLL). Based on the input frequency generated internally, the PLL provides the reference voltage for the converter to generate the desired voltage levels. To demonstrate the SIPO design concept, a voltage-mode boost DC-DC converter with a constant duty-cycle pulse control technique is implemented. For an input voltage of 1.5V, the boost converter is programmed to boost the output voltages to 2V to 4V over 90% power efficiency for the load currents ranged from 50mA to 300mA.