Chung-Jin Kim

Energy band engineered unified-RAM (URAM) for multi-functioning 1T-DRAM and NVM

A novel fusion memory is proposed as a new paradigm of silicon based memory technology. An O/N/O gate dielectric and a floating body are combined with a FinFET, and the non-volatile memory (NVM) and high speed capacitorless 1T-DRAM are performed in a single transistor. A nitride trap layer is used as an electron storage node for NVM, and hetero-epitaxially grown Si/Si1-xGex energy band engineered bulk substrates allow excess hole storage for 1T-DRAM. Highly reliable 1T-DRAM and NVM are demonstrated.

Gold nanoparticle embedded silicon nanowire biosensor for applications of label-free DNA detection

Gold nanoparticle (GN) embedded silicon nanowire (SiNW) configuration was proposed as a new biosensor for label-free DNA detection to enhance the sensitivity. The electric current flow between two terminals, a source and a drain electrode, were measured to sense the immobilization of probe oligonucleotides and their hybridization with target oligonucleotides. The complementary target oligonucleotide, breast cancer DNA with 1 pM, was sensed. In addition, its sensing mechanism and limit of detection (LOD) enhancement was investigated through simulation. The results support that the LOD can be improved by reducing the SiNW doping concentration. This emerging architecture combined nanostructure of spherical GN and SiNW has high potential as a label-free biosensor due to its facile fabrication process, high thermal stability, immobilization efficiency with a thiol-group in a self-assembled monolayer (SAM), and improved sensitivity.

Universal Potential Model in Tied and Separated Double-Gate MOSFETs With Consideration of Symmetric and Asymmetric Structure

A universal compact potential model for all types of double-gate MOSFETs is presented. An analytical closed-form solution to a 2D Poissons equation is obtained with the approximation that a vertical channel potential distribution is a cubic function of position. As a result, an analytical equation for the threshold voltage is derived from the proposed potential model. Different gate work functions and independent gate biases for front and back gates are considered, and the proposed model is found to be valid for an arbitrary double-gate structure: a symmetric versus asymmetric double gate and a tied versus separated double-gate structure. The threshold voltage behaviors for double-gate MOSFETs are investigated for various device dimensions. The back-gate effects of the separated double gate are also investigated for various silicon channel thicknesses and gate oxide thicknesses. Last, a process-induced threshold voltage fluctuation is estimated for symmetric and asymmetric separated double-gate MOSFETs. The analytical solution of the threshold voltages is verified by a comparison with simulation results in terms of the gate length, the silicon thickness, and the gate oxide thickness. A good agreement between two sets of results is obtained.

A Bulk FinFET Unified-RAM (URAM) Cell for Multifunctioning NVM and Capacitorless 1T-DRAM

A bulk FinFET-based unified-RAM (URAM) cell technology is demonstrated for the fusion of a nonvolatile-memory (NVM) and capacitorless 1T-DRAM. An oxide/nitride/oxide layer and a floating-body are combined to perform a URAM operation in a single transistor. A buried n-well technology for NMOS allows hole accumulation for the 1T-DRAM operation in a p-type bulk substrate. The bulk FinFET URAM offers a cost-effective and fully compatible process with a conventional FinFET SONOS, and it also expedites heat dissipation. Highly reliable NVM and high-speed 1T-DRAM operation are confirmed, and it was also verified that there is no disturbance between the two memory functions.

Silicon Nanowire All-Around Gate MOSFETs Built on a Bulk Substrate by All Plasma-Etching Routes

A gate length of 25 nm and a silicon nanowire (SiNW) with a width of 6 nm and a height of 10 nm fully surrounded by a gate are demonstrated. A suspended SiNW, which is fully depleted, is fabricated on a bulk substrate by employing the deep reactive-ion etching process known as the Bosch process. The electrical characteristics and short-channel effects (SCEs) of the SiNW MOSFETs with all-around gates are presented. The fabricated devices show excellent immunity against SCEs despite their being built on a bulk substrate and having gate lengths scaled down to the 25-nm regime. Improved electrostatic characteristics that suppress the SCEs are shown when the dimension of the SiNW is reduced.

Enhancement of soft x-ray emission from a cryogenically cooled Ar gas jet irradiated by 25 fs laser pulse

Soft x-ray spectra (40–180 A) produced by the interaction of 25 fs laser pulses at an intensity of ∼7×1016 W/cm2 with a cryogenically cooled Ar gas jet have been measured. New spectral lines from Ar8+ and Ar9+ charge states appeared with decreasing gas temperature. Nonlinear increase of x-ray line emission from Ar7+, Ar8+, and Ar9+ was observed with cooling, which saturated below certain temperature. The drastic change in the spectrum is attributed to efficient collisional heating and collisional ionization of growing (102–103 atoms) Ar clusters from the cooled jet.

A Unified-RAM (URAM) Cell for Multi-Functioning Capacitorless DRAM and NVM

A novel partially-depleted (PD) SONOS FinFET is demonstrated for unified function of a high speed capacitorless IT-DRAM and non-volatile memory (NVM). A floating body and O/N/O layer are combined in a single FinFET to provide multi-functional unified-RAM (URAM) operation. The fabricated URAM shows a VT window of 3 V with a retention time exceeding 10 years for NVM operation and a sensing margin of 9 muA with a program/erase time of 10 nsec for IT-DRAM operation in a single memory cell transistor.

Fullerene-Derivative-Embedded Nanogap Field-Effect-Transistor and Its Nonvolatile Memory Application†

Adeviceplatformwithnanochannels,fabricatedbyeithertopdown or bottom-up nanofabrication technologies, has been attracting notable attention in various fields and applications. Asarepresentativecaseofsuchnanochanneldeviceplatform,a nanogap- embedded field-effect-transistor (FET) has shown a great potential as a fast and label-free detection tool for a specific target material by monitoring the changes in electrical characteristicssuchasthethresholdvoltageorconductivity. [1,2] In a recent publication, for example, we reported that the nanogap-embedded FET can detect biomolecules in a very sensitive way by confining them within the nanogap and by monitoring the induced change in the effective dielectric constant of gate dielectrics, which is directly tied to the threshold voltage of the FET under study. [1] Alternatively, a conductivity change that was induced upon bridging the gap with a conductive nanomedium was used as an unlabeled biosensor. [3,4] Inthosedevices,itisoftendifficulttoconfirmina

Gate-to-Source/Drain Nonoverlap Device for Soft-Program Immune Unified RAM (URAM)

A soft-program immune structure for a unified RAM (URAM) is presented. A unique feature of URAM is the multifunctionality of a flash and capacitorless 1T-DRAM in a single transistor. However, charge trapping into O/N/O during a cyclic 1T-DRAM operation can cause an undesirable threshold voltage shift, resulting in an unstable URAM operation called a soft program. In a gate-to-source/drain nonoverlap structure with a nonextended O/N/O layer under the gate spacer, the impact ionization region is steered out from the gate, which is located under the spacer. In the 1T-DRAM mode of URAM, the programming biases are selected so that impact ionization can occur under the gate spacer, thereby alleviating the soft program. The nonoverlap device relieves the operational voltage constraint imposed by the soft program. In addition, nonvolatile flash memory and capacitorless 1T-DRAM perform an acceptable performance without interference.

Band offset FinFET-based URAM (Unified-RAM) built on SiC for multi-functioning NVM and capacitorless 1T-DRAM

A FinFET-based unified-RAM (URAM) using the band offset of Si/SiC is demonstrated for the fusion of a non-volatile memory (NVM) and capacitorless 1T-DRAM operation. An oxide/nitride/oxide (O/N/O) gate dielectric and a floating body caused by the band offset are combined in a bulk FinFET to allow two memory operations in a single transistor. The device is fabricated on an epitaxially grown Si/SiC substrate and its process is fully compatible with a conventional bulk FinFET SONOS. Highly reliable NVM and high speed 1T-DRAM operation are confirmed in a single URAM cell.