Yung-Pin Lee

A new block-matching criterion for motion estimation and its implementation

A novel and efficient block-matching motion estimation criterion called minimized maximum error (MiniMax) is considered. The proposed method can save hardware area about 15% with acceptable video performance. A chip which combines the MiniMax matching criterion and the one-dimensional full search algorithm is presented. The ASIC is motivated by the need of the intensive computational demand to perform motion estimation in real time. The proposed single chip can match the applications of H.261 and MPEG international standards. Chip cascading is allowed for larger searching range applications. >

A cost-effective architecture for 8/spl times/8 two-dimensional DCT/IDCT using direct method

Among the various transform techniques for image compression, the discrete cosine transform (DCT) is the most popular and effective one in practical image and video coding applications, such as high-definition television (HDTV). We develop a novel 8/spl times/8 two-dimensional (2-D) discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) architecture based on the direct 2-D approach and the rotation technique. The computational complexity is reduced by taking advantage of the special attribute of a complex number. Both the parallel and the folded architectures are proposed. Unlike other approaches, the proposed architecture is regular and economically allowable for VLSI implementation. Compared to the row-column method, less internal wordlength is needed in order to meet the error requirement of IDCT, and the throughput of the proposed architecture can achieve two times that of the row-column method with 30% hardware increased.

A real-time video signal processing chip

A real-time video signal processing chip for video data compression which combines block truncation coding (BTC) and a conventional motion compensation (MC) algorithm is presented. The regularity and simplicity of the BTC algorithm strongly suggest that it is quite suitable for an efficient VLSI implementation. It is shown that the proposed BTC-based system is much better than the conventional system in terms of implementation, complexity, and accuracy. Two benchmark sequences are used as test examples. The clock rate of the designed chip is about 47 MHz, which is suitable for most video applications. >

Low power 2D DCT chip design for wireless multimedia terminals

In this paper, a low power 2-D DCT architecture based on direct 2-D approach is proposed. The direct 2-D consideration reduces computational complexity. According to this algorithm, a parallel distributed arithmetic (DA) architecture at reduced supply voltage is derived. In the real circuit implementation of the chip, an adder of low power consumption is designed, as well as a power-saving ROM and a low voltage two-port SRAM with sequential access. The resultant 2-D DCT chip is realized by 0.6 /spl mu/m single-poly double-metal technology. Critical path simulation indicates a maximum input rate of 133 MHz, and it consumes 138 mW at 100 MHz.

A low power 2D DCT chip design using direct 2D algorithm

In this paper, a low power 8/spl times/8 2D DCT architecture based on direct 2D approach is proposed. The direct 2D consideration reduces computational complexity. According to this algorithm, a parallel distributed arithmetic (DA) architecture at reduced supply voltage is derived. In the real circuit implementation of the chip, a hybrid-architecture adder of low power consumption is designed, as well as a power-saving ROM and a low voltage two-port SRAM with sequential access. The resultant 2D DCT chip is realized by 0.6 /spl mu/m single-poly double-metal technology. Critical path simulation indicates a maximum input rate of 133 MHz, and it consumes 138 mW at 100 MHz.

A novel video signal processor with programmable data arrangement and efficient memory configuration

This paper describes a novel video signal processor (VSP) with a fully pipelined parallel architecture for video browsing, coding, and image processing for multimedia systems. The efficiency of the architecture developed is increased by use of a programmable data arrangement and an intelligent memory configuration. Techniques for reducing the interconnections and external memory accesses are also presented. A configuration of random-access on-chip memory modules solves the problems of chip I/O and memory bandwidth requirement. Due to the properties of low cost, high speed, and low memory bandwidth requirements, the VSP provides efficient solutions for video signal processing applications.

A flexible data-interlacing architecture for full-search block-matching algorithm

This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on some cascading strategies, the same chips can be flexibly cascaded for different block sizes, search ranges, and pixel rates. In addition, the cascading chips can efficiently reuse data to decrease external memory accesses and achieve a high throughput rate. Our results demonstrate that the architecture with 2-D data-reuse is a flexible, low-pin-counts, high-throughput, and cascadable solution for full search block-matching algorithm.

A pseudo-object-oriented very low bit-rate video coding system with cache VQ for detail compensation

A pseudo object-oriented video coding system is proposed and implemented. In order to increase the coding efficiency, a cache VQ algorithm is suggested to further compress those areas where motion estimation fails. According to our primary simulation results, the visual quality of long-timed sequences is still acceptable even for bit-rates below 10 kbps. In addition to the high compression ratio for very low bit-rates, content-based applications are also expected since the proposed system utilizes the segmented motion field; furthermore, the occurrences of prediction errors generally locate at emotionally important parts, e.g. eyes and mouth, etc. All the coded components are not only useful for compression but also meaningful for video recognition.

Building a pseudo object-oriented very low bit-rate video coding system from a modified optical flow motion estimation algorithm

A modified optical flow algorithm (MOFA) is proposed for the development of a very low bit-rate video coding system. Another edge preserving constraint and pyramid approach are suggested to generate an accurate motion field and reduce the possibility of being trapped in a local minimum. Post-processing schemes are also designed to eliminated the problems for special regions. Compared with other motion estimation algorithms, the proposed method gives a more exact estimation in terms of the PSNR and subjective view. The arbitrarily shaped transform of the motion field is then selected to further remove the spatial redundancy. According to some primary simulation results, most of the test sequences are compressed into 16 kbps or lower with excellent picture quality.

Efficient hierarchical motion estimation algorithm based on visual pattern block segmentation

A new hierarchical block-matching motion estimation algorithm with the segmentation of variable block size and visual pattern is presented. The block partition with visual patterns which exploits the properties of the human visual systems (HVS) is employed to get a more precise motion estimation for the detailed regions with complex motion in an image. The hierarchical search expedites the motion estimation and simplifies the processing of the stationary area. Simple control overhead and low side information are required due to the regular decomposition of visual pattern structures. The performance of proposed method is superior over the conventional full search block-matching motion estimation while reducing computational complexity drastically. Extensive experimental results are included in this paper.