Mei-Juan Chen

Error concealment of lost motion vectors with overlapped motion compensation

Most video sequence coding systems use block motion compensation to remove temporal redundancy for video compression due to the regularity and simplicity. A new error concealment algorithm for recovering the lost or erroneously received motion vectors is presented. It combines the overlapped motion compensation and the side match criterion to make the effect of lost motion vectors subjectively imperceptible. The side match criterion takes advantage of the spatial contiguity and interpixel correlation of image to select the best-fit replacement among the motion vectors of spatially contiguous candidate blocks. Particularly, to mask the blocking artifacts, we incorporate an overlapping technique to create a subjectively closer approximation to the true error-free image.

One-dimensional full search motion estimation algorithm for video coding

A new hardware-oriented algorithm called the one-dimensional full search (1DFS) is presented for block-matching motion estimation in video compression. The simulation for this algorithm follows H.261 and MPEG international standards. In MPEG simulation, structures with 1-, 2- and 3-frame interpolation are compared. The performance of 1DFS is superior to that of other fast search algorithms. And it has more regular data flow, data reuse and less control overhead. It is an alternative for 2D full search block matching and achieves a good compromise between computational complexity and performance. With competent performance and reasonable computation complexity, the proposed method is more suitable for real-time hardware realization of a VLSI motion estimator for video applications. >

A new block-matching criterion for motion estimation and its implementation

A novel and efficient block-matching motion estimation criterion called minimized maximum error (MiniMax) is considered. The proposed method can save hardware area about 15% with acceptable video performance. A chip which combines the MiniMax matching criterion and the one-dimensional full search algorithm is presented. The ASIC is motivated by the need of the intensive computational demand to perform motion estimation in real time. The proposed single chip can match the applications of H.261 and MPEG international standards. Chip cascading is allowed for larger searching range applications. >

A cost-effective architecture for 8/spl times/8 two-dimensional DCT/IDCT using direct method

Among the various transform techniques for image compression, the discrete cosine transform (DCT) is the most popular and effective one in practical image and video coding applications, such as high-definition television (HDTV). We develop a novel 8/spl times/8 two-dimensional (2-D) discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) architecture based on the direct 2-D approach and the rotation technique. The computational complexity is reduced by taking advantage of the special attribute of a complex number. Both the parallel and the folded architectures are proposed. Unlike other approaches, the proposed architecture is regular and economically allowable for VLSI implementation. Compared to the row-column method, less internal wordlength is needed in order to meet the error requirement of IDCT, and the throughput of the proposed architecture can achieve two times that of the row-column method with 30% hardware increased.

Error concealment algorithm using interested direction for JPEG 2000 image transmission

Digital image transmission is widely used in consumer products, e.g., digital camera and cellular phone, etc. The newly defined JPEG 2000 delivers image with lower bit rate in the Internet and wireless communications. However, JPEG 2000 decoding is processed bitplane by bitplane. Any data loss in bitstream affects the consequent bitplanes and even possible destroy the whole picture. We propose a new algorithm to recover the damaged bitplanes data according to the interested directional sets (IDS) of in-subband. The proposed algorithm is quite simple, but is very efficient in concealing the loss data of any subband in streaming real-time video data in the Internet and wireless communications. The simulation results show that the proposed algorithm has 1.5-3dB improvements than previously presented error resilient mechanism. In a subjective view, the proposed concealment algorithm can achieve much smoother edges on the reconstructed images.

Robust error concealment algorithm for MPEG-4 with the aid of fuzzy theory

A new error concealment algorithm based on fuzzy set theory is proposed to repair damaged portions of the shape information. By the experiment results, the proposed algorithm has better performance than previous works especially on the case that the damaged portion includes the edge of object.

A novel video signal processor with programmable data arrangement and efficient memory configuration

This paper describes a novel video signal processor (VSP) with a fully pipelined parallel architecture for video browsing, coding, and image processing for multimedia systems. The efficiency of the architecture developed is increased by use of a programmable data arrangement and an intelligent memory configuration. Techniques for reducing the interconnections and external memory accesses are also presented. A configuration of random-access on-chip memory modules solves the problems of chip I/O and memory bandwidth requirement. Due to the properties of low cost, high speed, and low memory bandwidth requirements, the VSP provides efficient solutions for video signal processing applications.

An I-phone system design and implementation with a portable speech coding coprocessor

This paper presents a high quality, low bit rate, and portable Internet-phone system. The system consists of a mixed implementation of software and hardware. The hardware includes a portable box that can be plugged into the conventional parallel port. Three major parts are considered in this box: the speech compression unit, the host interface, and the speakerphone module. A low-cost non-delicate speech coprocessor is embedded to process the heavy job of speech coding, a CPLD device is employed to control the host access timing, a 16-bit PCM codec and an audio amplifier with acoustic echo cancellation features are introduced to optimize the speakerphone module. The experimental coding rate is 8.5 kbps. At such a rate, the popular modems can conform to offer full-duplex speech in real time. Modern applications of this system include digital simultaneous voice data (DSVD) transmission, such as net-games talking and video-conferencing.

Error resilience for block loss with overlapped motion compensation

A new error resilience algorithm for recovering the lost blocks or motion vectors is presented. It combines the overlapped motion compensation and the side match criterion to make the effect of lost blocks subjectively imperceptible. The side match criterion takes advantage of the spatial contiguity and interpixel correlation of image to select the best-fit replacement among the motion vectors of spatially contiguous candidate blocks. Particularly, to mask the blocking artifacts, we incorporate an overlapping technique to create a subjectively closer approximation to the true error-free image.

A very low bit rate video coding system using adaptive region-classified vector quantization

In this paper, a new video coding algorithm suitable for the very low bit rate video application is presented. It takes advantage of the prior knowledge of the image type to segment the image into different regions, then codes each region with different coding criterion and method according to the different importance. An adaptive region-classified vector quantization strategy is also exploited in this algorithm. With the segmentation of the frame and high correlation between frames, better codebooks of vector quantisation are constructed to improve the quality. According to the simulation results, acceptable quality at about 10 kbit/s can be obtained for the typical test sequences.