Shuangfu Wang

Wafer-Level Packaging Design With Through Substrate Grooves as Interconnection for GaAs-Based Image Sensor

A wafer-level packaging design for GaAs-based image sensor is presented. Key processes, such as GaAs/glass wafer bonding, GaAs substrate thinning, through substrate grooves (TSGs) fabrication, redistribution layer formation, polymer passivation, and laser jet bumping, are examined and characterized. GaAs image sensor package with 64 leads is successfully fabricated on 4-in thinned GaAs/glass test vehicle wafer. In the package, two long TSGs are wet etched as the interconnection path. Process parameters are systematically studied and given. Then, fabrication results of these processes were discussed. Finally, electrical tests show that ohmic contact is obtained with a resistance of around 30 Ω between two nearby interconnections.

System integration for miniature node of wireless sensor network (WSN)

A type of 3D-SiP (System in Package) package for wireless sensor network (WSN) node was designed and developed based on an embedded FR-4 substrate using 3D technology (including, embedded way and stacked way) and SiP technology. The 3D-SiP package including sensor (sound or vibration) module, baseband ASIC chips, digital signal processor (DSP) chips, other chips and various passive components, was studied. FCOB (flip-chip on board), COB (chip on board), BGA technologies, wire bonding flip-chip bonding and surface mount (SMT) etc. interconnection technologies were combined together. Several kinds of solder materials with different melting points were used for initial and final vertical interconnections for the sake of compatibility of all levels interconnections by reflowing. High density WSN node with ASIC chip embedded in and sensor module stacked on high density multi-layer FR-4 substrate was designed and manufactured. The thermal management was conducted and the thermal related reliability of 3D-SiP were simulated and evaluated respectively.

Adhesive wafer bonding of GaAs/Glass with Benzocyclobutene and dry film for GaAs CCD

This paper studies adhesive wafer bonding of 4 inches GaAs CCD device wafer with Optik glass for wafer level packaging. In this work, Benzocyclobutene (BCB) and dry film (DF) were proposed as the bonding material. Efforts were devoted to the warpage control. The relationship between the extent of warpage and bonding parameters, such as the bonding profile, the thickness of bonding material, supporting wafer, were studied. The total bonding area and bonding strength were also studied. Under the optimized bonding conditions, warpage of 90.40 um was obtained for BCB bonding. The optimized condition was demonstrated. Nearly 100% bonding area was obtained for BCB bonding. For DF bonding, the warpage was 123.47. The bonding strength was 15.89 MPa for DF bonding.

Warpage characteristics of wafer-level package of MEMS with glass frit bonding

Warpage is one of the challenging problems for wafer level package (WLP). Especially, the bonding process of multiple wafers will bring additional stress to WLP and warpage of WLP. This paper aims at the stress and warpage characteristics of the WLP (consisting of silicon cover wafer and silicon MEMS wafer) with glass frit bonding. The finite element (FE) method and MOS (Multi-beam Optical Sensor) technology were used. Simulation result indicated that WLP presents almost zero warpage. MOS measurement result indicated that WLP actually presents convex warpage instead of zero warpage. It turned out that the convex warpage results from the temperature difference between WLP wafers (i.e. cover wafer and MEMS wafers) in the course of post-bond cooling. Taken the temperature difference into account, the simulation result was consistent with experiment results. Furthermore, on the basis of the convex warpage value the stress of WLP was also calculated so as to understand the stress distribution and estimate the reliability level of the MEMS device.

Wafer level packaging for GaAs optical detector using through wafer grooves (TWG) fabricated by mechanical dicing and wet etching

This paper reported a wafer level packaging (WLP) of GaAs optical detector, of which the packaging structure is featured by a Through Wafer Groove (TWG) fabricated by using a combined methodology of both mechanical dicing and wet chemical etching. This fabrication approach had the advantage of low process temperature (under 250 °C), low cost, no ion bombardment damage, and good uniformity. The packaging structure and the fabrication process were presented, and the results were discussed. Besides, the electrical connection was tested, which showed a high reliability.

Suspended of high-Q integrated inductors using wafer level packaging technologies

Thin film multilayer technologies adapted from wafer level packaging offer a very promising approach for the implementation of integrated passive devices, which have become increasingly popular these years. In this paper, we present a novel fabrication technique which combines wafer level packaging (WLP) and Micro-Electro-Mechanic System (MEMS) technologies to prepare suspended inductors with high Q factor. Simulation and measurement of both the proposed suspended inductors and non-suspended ones on low resistivity silicon wafers are done. The measured quality factor (Q) of 5.6nH suspended inductors with optimal strictures fabricated using polyimide (PI)/copper (Cu) thin film technology and two step etching are significantly higher than the traditional PI/Cu inductors.

Fabrication of deep vias/grooves as interconnection path by wet etching for wafer level packaging of GaAs based image sensor

GaAs wet etching was utilized for through substrate vias/grooves fabrication in wafer level packaging of GaAs based image sensor. In this work, GaAs wet etching was carried out on (100)-oriented substrates with PR mask as well as SiO₂ mask. Three kinds of etching system i.e. (A) 1H₂SO₄ + 8H₂O₂ + 1H₂O, (B) 9H₃PO₄ + 1H₂O₂ + 20H₂O, (C) 1K₂Cr₂O₇ + 1HBr + 4CH₃COOH are tested at room temperature. Mask pattern of different shapes, dimensions and orientations for vias and grooves were designed. The etching for deep grooves was also carried out on thinned GaAs/Glass bonding substrate from the back side of the device. And some critical issues and problems were also discussed.

A combined fabrication methodology of the through wafer via for wl-package of GaAs image sensors

As an image sensor material, Gallium Arsenide (GaAs) has its advantages over Silicon, such as high speed and high sensitivity, and can be applied in many areas. However, little work has been reported about the packaging of GaAs image sensors, especially at wafer level. The fabrication of the through wafer interconnection structure in GaAs wafer is a key process. In this paper a new combined fabrication method of preparing the through wafer via was proposed and investigated. The fabrication method includes the optimal combination of mechanical cutting by dicing blades and wet chemical etch. The prepared via or trench was 100um in depth, and had smooth surface by which a metal layer served as through wafer interconnection could be realized.