Chunyu Xin

A 3-V, 0.35-/spl mu/m CMOS Bluetooth receiver IC

This paper presents a monolithic low-IF Bluetooth receiver. The highlights of the receiver include a low-power active complex filter with a non-conventional tuning scheme and a high performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25 mm/sup 2/ die using TSMC 0.35 /spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 BER, -10 dBm IIP3 and 15 dB noise figure were achieved In the measurements.

A GFSK demodulator for low-IF Bluetooth receiver

An efficient mixed-mode Gaussian frequency-shift keying (GFSK) demodulator with a frequency offset cancellation circuit is presented. The structure is suitable for a low-IF Bluetooth receiver and can also be applied to other receivers involving continuous phase shift keying (CPSK) signals. The demodulator implementation is robust to tolerate process variations without requiring calibration. It can also track and cancel the time-varying local oscillator frequency offset between transmitter and receiver during the entire reception period. The chip was fabricated in CMOS 0.35-/spl mu/m digital process; it consumes 3 mA from a 3-V power supply and occupies 0.7 mm/sup 2/ of silicon area. A 16.2-dB input signal-to-noise ratio is obtained to achieve 0.1% bit-error rate as specified in Bluetooth specs. The co-channel interference rejection ratio is about 11 dB. Theoretical and experimental results are in good agreement.

A linearization technique for RF low noise amplifier

A LNA linearization technique derived from multi-gated configuration using bipolar transistors in CMOS technology is proposed. A bipolar transistor is used to replace the auxiliary MOS transistor to achieve higher operational speed. Both single-ended and differential applications are investigated. Simulation shows that this method is competitive with already reported low noise amplifiers. For 3 GHz of frequency operation, the single-ended structure achieves +15 dBm IIP3 with 8.9 mW power consumption, and the differential architecture can achieve +14 dBm IIP3 with 21 mW power consumption.

Chameleon: a dual-mode 802.11b/Bluetooth receiver system design

In this paper, an approach to map the Bluetooth and 802.11b standards specifications into an architecture and specifications for the building blocks of a dual-mode direct conversion receiver is proposed. The design procedure focuses on optimizing the performance in each operating mode while attaining an efficient dual-standard solution. The impact of the expected receiver nonidealities and the characteristics of each building block are evaluated through bit-error-rate simulations. The proposed receiver design is verified through a fully integrated implementation from low-noise amplifier to analog-to-digital converter using IBM 0.25-/spl mu/m BiCMOS technology. Experimental results from the integrated prototype meet the specifications from both standards and are in good agreement with the target sensitivity.

A GSM LNA using mutual-coupled degeneration

This letter presents a low noise amplifier (LNA) input impedance matching technique using mutual coupled inductors. This scheme not only provides the required input impedance matching but also interstage impedance transformation for the cascoded transistor. The mutual coupled inductors also help to improve the circuits reverse isolation. A 900-MHz global system for mobile communication LNA using this technique is designed and fabricated using 0.35-/spl mu/m standard complementary metal oxide semiconductor technology. It achieves a 17-dB gain, 3.4-dB noise figure, and -5.1-dBm IIP3. The LNA draws 5.6 mA from a single 2.3-V power supply.

A dual-mode 802.11b/Bluetooth receiver in 0.25/spl mu/m BiCMOS

A dual-mode direct-conversion 802.11b/Bluetooth receiver is integrated from LNA to ADC in a 0.25/spl mu/m BiCMOS process. The baseband circuits are programmable to accommodate both standards while the RF front-end is shared. Die area is 21 mm/sup 2/, and the IC consumes 45.6/41.3mA (802.11b/Bluetooth). Sensitivity is -86/-91dBm and IIP3 is -13/-13dBm.

A monolithic CMOS low-IF Bluetooth receiver

A fully integrated low-IF CMOS Bluetooth receiver is presented. The IC is fabricated in TSMC 0.35 /spl mu/m standard CMOS process. The receiver consists of a radio frequency (RF) front end, a phase lock loop (PLL), an active complex filter, a GFSK demodulator and a frequency offset cancellation circuit. The experimental results show a -82 dBm sensitivity at le-3 BER, -10 dBm IIP3 and 15 dB noise figure.

A mixed-mode IF GFSK demodulator for Bluetooth

The paper describes a novel mixed-mode GFSK demodulator with a frequency offset cancellation circuit as part of a low-IF Bluetooth receiver. The demodulator is fabricated in TSMC 0.35 /spl mu/m standard CMOS process, consumes 3 mA from a 3 V power supply and occupies 0.7mm/sup 2/ of silicon area. For 10/sup -3/ BER as specified in Bluetooth standard, only 16.2 dB input SNR is required. The co-channel interference rejection is about 11 dB. The demodulator is robust to process technology variation, and no calibration is required. It can track and cancel the time-varying local oscillator (LO) frequency offset between transmitter and receiver during the whole reception time.

A 3 V, 0.35 /spl mu/m CMOS Bluetooth receiver IC

This paper presents a monolithic low-IF Bluetooth receiver. The highlights of the receiver include a low-power active complex filter with a non-conventional tuning scheme and a high performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25 mm/sup 2/ die using TSMC 0.35 /spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 BER, -10 dBm IIP3 and 15 dB noise figure were achieved In the measurements.