Sung Tae Moon

A 3-V, 0.35-/spl mu/m CMOS Bluetooth receiver IC

This paper presents a monolithic low-IF Bluetooth receiver. The highlights of the receiver include a low-power active complex filter with a non-conventional tuning scheme and a high performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25 mm/sup 2/ die using TSMC 0.35 /spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 BER, -10 dBm IIP3 and 15 dB noise figure were achieved In the measurements.

High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters

Integrated DC-DC converters switching above 100MHz dramatically reduce the footprint of the inductors and capacitors while improving droop response. Unfortunately, such converters utilize advanced digital CMOS processes with the maximum input voltage below 2 V. We propose a fully integrated linear regulator that enables doubling of the converter input voltage by properly biasing stacked drivers and bridge transistors. By implementing fast digital control the linear regulator meets the transient current demand of the converter without resorting to off-chip decoupling capacitors. In a 90 nm CMOS process, the 2.4V input, 1.2 V output, linear regulator occupies 0.03 mm2 for a plusmn1 A rating. A 288 ps response time and 97.5% current efficiency result in a 2.84times improvement in speed-power figure of merit over previous work

Self-calibrated quadrature generator for WLAN multistandard frequency synthesizer

A self-calibrated quadrature generator capable of generating local oscillator (LO) outputs for IEEE 802.11a-b is presented. The quadrature generator is embedded in a frequency synthesizer that generates reference frequencies at 2.4 and 5GHz. A new sequential calibration scheme maintains the quadrature at the 5-GHz output within a maximum phase error of 2/spl deg/, while a divide-by-two flip-flop generates the quadrature output at 2.4 GHz. The circuit is fabricated in a 0.25-/spl mu/m SiGe BiCMOS technology and occupies a silicon area of 2 mm/sup 2/; the quadrature generator consumes a current of 5 mA from a 2.5-V supply.

A dual-mode 802.11b/Bluetooth receiver in 0.25/spl mu/m BiCMOS

A dual-mode direct-conversion 802.11b/Bluetooth receiver is integrated from LNA to ADC in a 0.25/spl mu/m BiCMOS process. The baseband circuits are programmable to accommodate both standards while the RF front-end is shared. Die area is 21 mm/sup 2/, and the IC consumes 45.6/41.3mA (802.11b/Bluetooth). Sensitivity is -86/-91dBm and IIP3 is -13/-13dBm.

A monolithic CMOS low-IF Bluetooth receiver

A fully integrated low-IF CMOS Bluetooth receiver is presented. The IC is fabricated in TSMC 0.35 /spl mu/m standard CMOS process. The receiver consists of a radio frequency (RF) front end, a phase lock loop (PLL), an active complex filter, a GFSK demodulator and a frequency offset cancellation circuit. The experimental results show a -82 dBm sensitivity at le-3 BER, -10 dBm IIP3 and 15 dB noise figure.

FULLY INTEGRATED FREQUENCY SYNTHESIZERS: A TUTORIAL

Frequency synthesizer is a key building block of fully-integrated wireless communications systems. Design of a frequency synthesizer (FS) requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. The FS design challenge involves strong trade-offs, and often conflicting requirements. In this tutorial, the general implementation issues and recent developments of frequency synthesizer design are discussed. Simplified design approach should provide readers with sufficient intuition for fast design and troubleshooting capability. Open problems in this FS field are briefly discussed.

Low Voltage Buffered Bandgap Reference

We propose a new bandgap reference topology for supply voltages as low as one diode drop (~0.8V). In conventional low-voltage references, supply voltage is limited by the generated reference voltage. Also, the proposed topology generates the reference voltage at the output of the feedback amplifier. This eliminates the need for an additional output buffer, otherwise required in conventional topologies. With the bandgap core biased from the reference voltage, the new topology is also suitable for a low-voltage shunt reference. We fabricated a 1V, 0.35mV/degC reference occupying 0.013mm2 in a 90nm CMOS process

A 3 V, 0.35 /spl mu/m CMOS Bluetooth receiver IC

This paper presents a monolithic low-IF Bluetooth receiver. The highlights of the receiver include a low-power active complex filter with a non-conventional tuning scheme and a high performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25 mm/sup 2/ die using TSMC 0.35 /spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 BER, -10 dBm IIP3 and 15 dB noise figure were achieved In the measurements.