Ari Yakov Valero-Lopez

A 3-V, 0.35-/spl mu/m CMOS Bluetooth receiver IC

This paper presents a monolithic low-IF Bluetooth receiver. The highlights of the receiver include a low-power active complex filter with a non-conventional tuning scheme and a high performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25 mm/sup 2/ die using TSMC 0.35 /spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 BER, -10 dBm IIP3 and 15 dB noise figure were achieved In the measurements.

A GFSK demodulator for low-IF Bluetooth receiver

An efficient mixed-mode Gaussian frequency-shift keying (GFSK) demodulator with a frequency offset cancellation circuit is presented. The structure is suitable for a low-IF Bluetooth receiver and can also be applied to other receivers involving continuous phase shift keying (CPSK) signals. The demodulator implementation is robust to tolerate process variations without requiring calibration. It can also track and cancel the time-varying local oscillator frequency offset between transmitter and receiver during the entire reception period. The chip was fabricated in CMOS 0.35-/spl mu/m digital process; it consumes 3 mA from a 3-V power supply and occupies 0.7 mm/sup 2/ of silicon area. A 16.2-dB input signal-to-noise ratio is obtained to achieve 0.1% bit-error rate as specified in Bluetooth specs. The co-channel interference rejection ratio is about 11 dB. Theoretical and experimental results are in good agreement.

Self-calibrated quadrature generator for WLAN multistandard frequency synthesizer

A self-calibrated quadrature generator capable of generating local oscillator (LO) outputs for IEEE 802.11a-b is presented. The quadrature generator is embedded in a frequency synthesizer that generates reference frequencies at 2.4 and 5GHz. A new sequential calibration scheme maintains the quadrature at the 5-GHz output within a maximum phase error of 2/spl deg/, while a divide-by-two flip-flop generates the quadrature output at 2.4 GHz. The circuit is fabricated in a 0.25-/spl mu/m SiGe BiCMOS technology and occupies a silicon area of 2 mm/sup 2/; the quadrature generator consumes a current of 5 mA from a 2.5-V supply.

Chameleon: a dual-mode 802.11b/Bluetooth receiver system design

In this paper, an approach to map the Bluetooth and 802.11b standards specifications into an architecture and specifications for the building blocks of a dual-mode direct conversion receiver is proposed. The design procedure focuses on optimizing the performance in each operating mode while attaining an efficient dual-standard solution. The impact of the expected receiver nonidealities and the characteristics of each building block are evaluated through bit-error-rate simulations. The proposed receiver design is verified through a fully integrated implementation from low-noise amplifier to analog-to-digital converter using IBM 0.25-/spl mu/m BiCMOS technology. Experimental results from the integrated prototype meet the specifications from both standards and are in good agreement with the target sensitivity.

A monolithic CMOS low-IF Bluetooth receiver

A fully integrated low-IF CMOS Bluetooth receiver is presented. The IC is fabricated in TSMC 0.35 /spl mu/m standard CMOS process. The receiver consists of a radio frequency (RF) front end, a phase lock loop (PLL), an active complex filter, a GFSK demodulator and a frequency offset cancellation circuit. The experimental results show a -82 dBm sensitivity at le-3 BER, -10 dBm IIP3 and 15 dB noise figure.

FULLY INTEGRATED FREQUENCY SYNTHESIZERS: A TUTORIAL

Frequency synthesizer is a key building block of fully-integrated wireless communications systems. Design of a frequency synthesizer (FS) requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. The FS design challenge involves strong trade-offs, and often conflicting requirements. In this tutorial, the general implementation issues and recent developments of frequency synthesizer design are discussed. Simplified design approach should provide readers with sufficient intuition for fast design and troubleshooting capability. Open problems in this FS field are briefly discussed.

A mixed-mode IF GFSK demodulator for Bluetooth

The paper describes a novel mixed-mode GFSK demodulator with a frequency offset cancellation circuit as part of a low-IF Bluetooth receiver. The demodulator is fabricated in TSMC 0.35 /spl mu/m standard CMOS process, consumes 3 mA from a 3 V power supply and occupies 0.7mm/sup 2/ of silicon area. For 10/sup -3/ BER as specified in Bluetooth standard, only 16.2 dB input SNR is required. The co-channel interference rejection is about 11 dB. The demodulator is robust to process technology variation, and no calibration is required. It can track and cancel the time-varying local oscillator (LO) frequency offset between transmitter and receiver during the whole reception time.

Frequency synthesizer for on-chip testing and automated tuning

This paper presents a compact, phase-locked loop (PLL) based, frequency synthesizer suitable for built-in testing and automatic tuning applications operating in the 100 MHz frequency range. Key features of this design include a differential charge pump with common mode feedback (CMFB) and a voltage controlled oscillator (VCO) based on a pseudo-differential OTA with a linear transconductance control and tuning invariant output resistance. Experimental results from an integrated prototype fabricated using standard 0.35 /spl mu/m CMOS technology are presented. The measured HD3 of the output signal is better than -39 dB over 80% of the tuning range: 40-160 MHz. The circuit occupies a silicon area of 200/spl times/1000 /spl mu/m/sup 2/ and operates from a 3.3 V power supply.

A 3 V, 0.35 /spl mu/m CMOS Bluetooth receiver IC

This paper presents a monolithic low-IF Bluetooth receiver. The highlights of the receiver include a low-power active complex filter with a non-conventional tuning scheme and a high performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25 mm/sup 2/ die using TSMC 0.35 /spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 BER, -10 dBm IIP3 and 15 dB noise figure were achieved In the measurements.

Efficient clock recovery architecture

In this paper, a clock recovery architecture is proposed. Although it employs a single high frequency loop, the structure behaves as the typical double loop clock recovery system. The proposed topology uses a high frequency phase detector, a low frequency loop and avoids the use of quadrature VCOs.