Ciby Thuruthiyil

Extraction of Self-Heating Free I-V Curves Including the Substrate Current of PD SOI MOSFETs

A new methodology is proposed to extract self-heating free I-V curves, including the substrate current, of SOI MOSFETs based on triple-temperature, regular DC measurement. It is verified to be accurate with Hspice simulations and suitable for SPICE model parameter extraction. It is also demonstrated that extraction of self-heating free I-V curves is not only desired for efficient SPICE model generation, but also required to accurately capture the true temperature dependences in the models.

Statistical Compact Modeling and Si Verification Methodology

As we scale down to sub-65nm technologies, transistors and interconnects no longer act as predictable elements, but start acting as statistical blocks due to static and dynamic variations. This invited paper first reviews some of the key variations that need to be considered for any statistical analysis. Also, details for implementing statistical models into compact modeling flow are discussed. Finally, the paper reviews one of the techniques used for generating and validating statistical models with the silicon data

Critical current (I CRIT ) based SPICE model extraction for SRAM cell

Critical currents (ICRIT) extracted from the N-curves of a 6-T SRAM bit cell have been shown in recent research to be important and effective figures of merit for the cell¿s stability and write-ability. SPICE models of cell transistors, therefore, not only need to fit closely to individual transistor¿s I-V characteristics, but also faithfully reproduce ICRITs¿ behavior of the cell as a whole. A branch current analysis is performed to reveal individual transistors¿ impact on ICRITs¿ and their key bias regions. Based on the insight from the analysis, an efficient SPICE model extraction flow is proposed that enables decoupled fine tuning of the pass-gate, pull-down, and pull-up transistor models to achieve satisfactory fit to ICRITs without model extraction iterations.

Extraction of speculative SOI MOSFET models using self-heating-free targets

Speculative SPICE models (also referred to as evaluation-level or guess models), which are extracted based on projected device electrical characteristics (called `targets¿) rather than actual measurement data, are required to support concurrent IC designs. The self-heating effect in silicon-on-insulator (SOI) technologies presents additional challenges in obtaining quality speculative SOI MOSFET models. A novel `shift-and-ratio¿ technique is developed to generate self-heating free device targets from raw targets provided only at room temperature, and a corresponding speculative model extraction methodology is proposed. The shift-and-ratio technique is validated by using silicon data of 65 nm partially-depleted (PD) SOI technologies. The adequacy and self-consistency of the speculative model extraction methodology is demonstrated in field testing where a large number of 65 nm and 45 nm PD SOI speculative models are extracted. Availability of self-heating free targets proves to be critical not only for improved speculative model extraction efficiency, but also for model quality in general by ensuring physical and reasonable temperature dependences in the resulting speculative models.

Off-state leakage current modeling in low-power/high-performance partially-depleted (PD) floating-body (FB) SOI MOSFETs

Off-state leakage current in a 65 nm partially depleted (PD) floating-body (FB) SOI technology is modeled and analyzed with emphasis on its drain-voltage dependence. Modeling accuracy of the off-state leakage current is highly dependent on modeling of parasitic currents, although their direct contribution to the leakage may be negligible in lower-power/high-performance technologies. The underlying physical mechanism, i.e., the FB effect, is also shown to be responsible for observed varying drain-induced-barrier-lowering (DIBL) or highly non-linear dependence of the threshold voltage on drain voltage. While characterization of parasitic currents may present a challenge because of unconventional geometry dependences, the off-state leakage current and its fitting accuracy may be used as an indirect, effective figure of merit.

Impact of stress on various circuit characteristics in 65nm PDSOI technology

Logic performance is improved by creating more stress in the channel in advanced CMOS technologies. Impact of stress on different circuit blocks in a microprocessor chip has not been studied in detail. This paper presents a comprehensive study on the effects of stress and the corresponding process steps on various circuit characteristics. Analog behavior, hysteresis and noise properties are investigated to understand the effect of stress on them. These characteristics play important roles in determining the performances of analog/phy, I/O and PLL blocks respectively. It is shown that the type of process steps used for stress optimization can significantly alter the performance of various circuits.