Judy Xilin An

BSIM4 gate leakage model including source-drain partition

Gate dielectric leakage current becomes a serious concern as sub-20 /spl Aring/ gate oxide prevails in advanced CMOS processes. Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance. While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage. In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed. This model has been implemented in BSIM4.

50 nm gate-length CMOS transistor with super-halo: design, process, and reliability

CMOS transistors with a 50 nm physical gate length are demonstrated. Super-halo, implemented by angle-tilted implantation, is utilized to control V/sub th/ roll-off down to a gate length of 40 nm. Super-halo also provides V/sub th/ adjustment as well as a retrograde channel to suppress subsurface body punch-through. 935 /spl mu/A//spl mu/m and 395 /spl mu/A//spl mu/m on-state drive currents were achieved for n- and p-channel MOSFETs, respectively, with a V/sub dd/ of 1.5 V. The I/sub drive//(C/sub ox(inv)/V/sub dd/) figure-of-merit (FOM) of the CMOS devices falls on the trend line extrapolated from existing industrial CMOS technologies. The impacts of super-halo on V/sub th/ roll-off, DIBL, gate overlap Miller capacitance and junction capacitance in a 50 nm MOSFET are investigated. Strong halo can result in drain-to-halo (body) band-to-band tunneling leakage even at room temperature. Degradation of gate oxide leakage and hot-carrier reliability due to large-angle-tilted halo implant are concerns in 50 nm CMOS transistors.

Impact of interfacial layer and transition region on gate current performance for high-K gate dielectric stack: its tradeoff with gate capacitance

Stacked gate dielectrics are modeled with respect to the impact on the leakage current of interfacial layers and transition regions, considering the tradeoff with the gate capacitance. A Franz 2-band dispersion model is used. Low-EOT and low-gate-current regimes are explored theoretically using reasonable estimates guided by experimental data. Transition layer values of each parameter are qualitatively explored for oxynitride, Si/sub 3/N/sub 4//SiO/sub 2/, and high-K stacks. Higher dielectric constant and more insulating materials are obviously desired for each layer of dielectric; however, the transition region becomes more important as such dielectrics are considered. Higher dielectric constant of interfacial layer is desirable for the low-EOT-low-gate-current requirement.

Efficient generation of pre-silicon MOS model parameters for early circuit design

The technology development cycle continues to shrink, which very often requires evaluation of circuit design and technology choices using circuit simulators at the time when no real silicon is available. In this paper, we present an efficient methodology for generating pre-silicon device models for advanced CMOS processes. The methodology allows accurate prediction of the full MOS I-V characteristics for the future technologies combining a constraint backpropagation algorithm based upon a few critical specifications, physical models for the advanced device phenomena, and the empirical data from devices of an existing technology. The methodology has been tested on two CMOS production technologies. Good prediction results are achieved: for nMOS the rms error is 1%-2%, for pMOS it is 2%-4%.

Extraction of Self-Heating Free I-V Curves Including the Substrate Current of PD SOI MOSFETs

A new methodology is proposed to extract self-heating free I-V curves, including the substrate current, of SOI MOSFETs based on triple-temperature, regular DC measurement. It is verified to be accurate with Hspice simulations and suitable for SPICE model parameter extraction. It is also demonstrated that extraction of self-heating free I-V curves is not only desired for efficient SPICE model generation, but also required to accurately capture the true temperature dependences in the models.

Scaling towards 35 nm gate length CMOS

We report 35 nm gate length planar CMOS transistors with aggressively scaled gate equivalent oxide thickness (EOT). A nitride/oxynitride (N/O) stack was used as gate dielectric with EOT ranging from 12 /spl Aring/ down to 7 /spl Aring/. The impact of gate scaling on transistor performance, gate tunneling leakage, short-channel effect, and channel carrier mobility is investigated. Excellent control of short-channel effect is achieved for sub-50 nm gate length devices. CV/I delays of 0.89 ps for n-MOSFET and 1.8 ps for p-MOSFET are demonstrated at a supply voltage of 0.85 V.

Statistical Compact Modeling and Si Verification Methodology

As we scale down to sub-65nm technologies, transistors and interconnects no longer act as predictable elements, but start acting as statistical blocks due to static and dynamic variations. This invited paper first reviews some of the key variations that need to be considered for any statistical analysis. Also, details for implementing statistical models into compact modeling flow are discussed. Finally, the paper reviews one of the techniques used for generating and validating statistical models with the silicon data

Impact of stress on various circuit characteristics in 65nm PDSOI technology

Logic performance is improved by creating more stress in the channel in advanced CMOS technologies. Impact of stress on different circuit blocks in a microprocessor chip has not been studied in detail. This paper presents a comprehensive study on the effects of stress and the corresponding process steps on various circuit characteristics. Analog behavior, hysteresis and noise properties are investigated to understand the effect of stress on them. These characteristics play important roles in determining the performances of analog/phy, I/O and PLL blocks respectively. It is shown that the type of process steps used for stress optimization can significantly alter the performance of various circuits.

Advanced compact modeling of logic devices toward CMOS scaling limits

Sonic research work on advanced compact modeling of nonclassical logic devices is reviewed in this paper. Advanced logic devices toward CMOS scaling limits are ill so reviewed as background information so as to understand the physics and features demanded by the non-classical logic devices and thus the challenges of modeling these devices.