Ali B. Icel

Extending two-element capacitance extraction method toward ultraleaky gate oxides using a short-channel length

This letter demonstrates that the conventional two-element lumped model can provide valid capacitance-voltage (C-V ) characteristics for gate oxides with large tunneling current, if the gate length is reduced. The two-element models generally suffer from severe distortion of C-V due to tunneling current, resulting in poor oxide thickness extraction. The distortion can be suppressed using high frequencies in series model or using short gate lengths in parallel model. Considering instrument limits and manufacturability, however, the parallel model is more desirable. The distortion can be completely suppressed up to 10/sup 4/ A/cm/sup 2/ of tunneling current, using gate lengths shorter than 0.2 /spl mu/m in parallel model.

Extraction of Self-Heating Free I-V Curves Including the Substrate Current of PD SOI MOSFETs

A new methodology is proposed to extract self-heating free I-V curves, including the substrate current, of SOI MOSFETs based on triple-temperature, regular DC measurement. It is verified to be accurate with Hspice simulations and suitable for SPICE model parameter extraction. It is also demonstrated that extraction of self-heating free I-V curves is not only desired for efficient SPICE model generation, but also required to accurately capture the true temperature dependences in the models.

CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design

Stressors have been used since 90 nm technology to improve device performance to overcome the limitations of scaling. The stressors, including, - CPEN, TPEN, SMT, and e-SiGe to improve NMOS and PMOS drive current exhibit proximity dependence. In addition, unintentional stressors such as STI edge proximity introduce additional layout dependencies. Two devices with the same L and W can have significantly different drive strength depending on their surroundings. There have been limited studies to optimize the design layout to reduce the layout-dependent stress degradation. Circuit and layout designers have few tools they can use to quickly and effectively optimize the layout to reduce device degradation due to layout-dependent stress effects. In this paper, we present a comprehensive set of CAD utilities, and stress-related layout guidelines to optimize the layout for full custom macros to reduce the layout-dependent stress effects prior to doing full timing characterization, including stress effects.

Modeling local variation of low-frequency noise in MOSFETs via sum of lognormal random variables

In this paper, we investigate the geometry dependence for the local variation of low-frequency noise in MOSFETs via the sum of lognormal random variables. A compact model has been developed and applied to the measured data with excellent match, and therefore enables the coverage of low-frequency noise statistics in circuit design.

Near-threshold circuit variability in 14nm FinFETs for ultra-low power applications

Ultra low power (ULP) applications use supply voltage (Vdd) scaling as an effective way of reducing power. However, as Vdd is scaled near the threshold voltage (Vt), increased variability limits the minimum Vdd and power that can be realized. This paper outlines a Veff variability framework to capture the total delay variation seen in digital circuits and describes its applicability for near-threshold delay variability analysis. The low-voltage variability framework has been validated against 14nm-FinFET ring oscillator (RO) measurements.

Critical current (I CRIT ) based SPICE model extraction for SRAM cell

Critical currents (ICRIT) extracted from the N-curves of a 6-T SRAM bit cell have been shown in recent research to be important and effective figures of merit for the cell¿s stability and write-ability. SPICE models of cell transistors, therefore, not only need to fit closely to individual transistor¿s I-V characteristics, but also faithfully reproduce ICRITs¿ behavior of the cell as a whole. A branch current analysis is performed to reveal individual transistors¿ impact on ICRITs¿ and their key bias regions. Based on the insight from the analysis, an efficient SPICE model extraction flow is proposed that enables decoupled fine tuning of the pass-gate, pull-down, and pull-up transistor models to achieve satisfactory fit to ICRITs without model extraction iterations.

Test structures to quantify contact placement-impacted drain current variations

The difference in the number of contacts across different transistors and standard cells results in current variations across the channel. In this work, we present test structures to target this effect and characterize and quantify the impact on 45 nm SOI silicon. After comparing the impact of contact resistance between 65 nm and 45 nm silicon, we provide and analyze our 45 nm test structure results and provide a means to extract mean contact resistance from our test structures. We observe that impact due to contact resistance can be up to 10% for 45 nm, while it could have been of less importance (less than 4%) for 65 nm technology. Such test structures and methodology help us provide intrinsic device models in 45 nm without inaccuracies or resistive double counting that may be introduced due to placement-impacted contact resistance variations.

Extraction of speculative SOI MOSFET models using self-heating-free targets

Speculative SPICE models (also referred to as evaluation-level or guess models), which are extracted based on projected device electrical characteristics (called `targets¿) rather than actual measurement data, are required to support concurrent IC designs. The self-heating effect in silicon-on-insulator (SOI) technologies presents additional challenges in obtaining quality speculative SOI MOSFET models. A novel `shift-and-ratio¿ technique is developed to generate self-heating free device targets from raw targets provided only at room temperature, and a corresponding speculative model extraction methodology is proposed. The shift-and-ratio technique is validated by using silicon data of 65 nm partially-depleted (PD) SOI technologies. The adequacy and self-consistency of the speculative model extraction methodology is demonstrated in field testing where a large number of 65 nm and 45 nm PD SOI speculative models are extracted. Availability of self-heating free targets proves to be critical not only for improved speculative model extraction efficiency, but also for model quality in general by ensuring physical and reasonable temperature dependences in the resulting speculative models.

Off-state leakage current modeling in low-power/high-performance partially-depleted (PD) floating-body (FB) SOI MOSFETs

Off-state leakage current in a 65 nm partially depleted (PD) floating-body (FB) SOI technology is modeled and analyzed with emphasis on its drain-voltage dependence. Modeling accuracy of the off-state leakage current is highly dependent on modeling of parasitic currents, although their direct contribution to the leakage may be negligible in lower-power/high-performance technologies. The underlying physical mechanism, i.e., the FB effect, is also shown to be responsible for observed varying drain-induced-barrier-lowering (DIBL) or highly non-linear dependence of the threshold voltage on drain voltage. While characterization of parasitic currents may present a challenge because of unconventional geometry dependences, the off-state leakage current and its fitting accuracy may be used as an indirect, effective figure of merit.

Impact of stress on various circuit characteristics in 65nm PDSOI technology

Logic performance is improved by creating more stress in the channel in advanced CMOS technologies. Impact of stress on different circuit blocks in a microprocessor chip has not been studied in detail. This paper presents a comprehensive study on the effects of stress and the corresponding process steps on various circuit characteristics. Analog behavior, hysteresis and noise properties are investigated to understand the effect of stress on them. These characteristics play important roles in determining the performances of analog/phy, I/O and PLL blocks respectively. It is shown that the type of process steps used for stress optimization can significantly alter the performance of various circuits.