Sushant Suryagandh

Extraction of Self-Heating Free I-V Curves Including the Substrate Current of PD SOI MOSFETs

A new methodology is proposed to extract self-heating free I-V curves, including the substrate current, of SOI MOSFETs based on triple-temperature, regular DC measurement. It is verified to be accurate with Hspice simulations and suitable for SPICE model parameter extraction. It is also demonstrated that extraction of self-heating free I-V curves is not only desired for efficient SPICE model generation, but also required to accurately capture the true temperature dependences in the models.

CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design

Stressors have been used since 90 nm technology to improve device performance to overcome the limitations of scaling. The stressors, including, - CPEN, TPEN, SMT, and e-SiGe to improve NMOS and PMOS drive current exhibit proximity dependence. In addition, unintentional stressors such as STI edge proximity introduce additional layout dependencies. Two devices with the same L and W can have significantly different drive strength depending on their surroundings. There have been limited studies to optimize the design layout to reduce the layout-dependent stress degradation. Circuit and layout designers have few tools they can use to quickly and effectively optimize the layout to reduce device degradation due to layout-dependent stress effects. In this paper, we present a comprehensive set of CAD utilities, and stress-related layout guidelines to optimize the layout for full custom macros to reduce the layout-dependent stress effects prior to doing full timing characterization, including stress effects.

Extraction of speculative SOI MOSFET models using self-heating-free targets

Speculative SPICE models (also referred to as evaluation-level or guess models), which are extracted based on projected device electrical characteristics (called `targets¿) rather than actual measurement data, are required to support concurrent IC designs. The self-heating effect in silicon-on-insulator (SOI) technologies presents additional challenges in obtaining quality speculative SOI MOSFET models. A novel `shift-and-ratio¿ technique is developed to generate self-heating free device targets from raw targets provided only at room temperature, and a corresponding speculative model extraction methodology is proposed. The shift-and-ratio technique is validated by using silicon data of 65 nm partially-depleted (PD) SOI technologies. The adequacy and self-consistency of the speculative model extraction methodology is demonstrated in field testing where a large number of 65 nm and 45 nm PD SOI speculative models are extracted. Availability of self-heating free targets proves to be critical not only for improved speculative model extraction efficiency, but also for model quality in general by ensuring physical and reasonable temperature dependences in the resulting speculative models.

Impact of stress on various circuit characteristics in 65nm PDSOI technology

Logic performance is improved by creating more stress in the channel in advanced CMOS technologies. Impact of stress on different circuit blocks in a microprocessor chip has not been studied in detail. This paper presents a comprehensive study on the effects of stress and the corresponding process steps on various circuit characteristics. Analog behavior, hysteresis and noise properties are investigated to understand the effect of stress on them. These characteristics play important roles in determining the performances of analog/phy, I/O and PLL blocks respectively. It is shown that the type of process steps used for stress optimization can significantly alter the performance of various circuits.