Claire Richard

FlexCC2: An Optimizing Retargetable C Compiler for DSP Processors

The design of efficient compilers for embedded processors has emerged with the growing importance of embedded application-specific processors and DSPs in consumer, multimedia and communication applications. We present in this paper the FlexCC2 compiler. FlexCC2 is a retargetable compiler for embedded processors, part of the FlexWare embedded software development environment. Application specific processors often contain specific and dedicated features like specific instructions that traditional compilers hardly accommodate. In this context, compilers able to produce high quality code, both in size and performance while being easily retargetable and able to use processor specific instructions represent a particular competitive differentiation. FlexCC2 offers such a differentiation to its users.

Barrier and Copper Seedlayer Wet Etching

This paper summarizes the process development of TiN barrier etching in presence of copper, for a thick copper level in BICMOS technology. In an industrial context, we have chosen to use a SC1 chemistry in a spin etch single wafer tool. The SC1 composition and therefore the pH level allows - the barrier to be etched with no metallic residues, ( if not clear this can be a source for shorts) - control of the selectivity between copper and TiN - control of lateral etching under copper lines, the possible source of open chains by W attack during TiN etch. The electrical results show a robust process according to current specifications, in terms of leakage and via resistance with a fresh chemistry approach. In fact, the recirculation of SC1 is not possible due to substantial concentration changes during processing, high evaporation rate of Ammonia and high decomposition rate of Peroxide in the presence of copper on surface wafer.

DAPHNE silicon photonics technological platform for research and development on WDM applications

A new technological platform aimed at making prototypes and feasibility studies has been setup at STMicroelectronics using 300mm wafer foundry facilities. The technology, called DAPHNE (Datacom Advanced PHotonic Nanoscale Environment), is devoted at developing and evaluating new devices and sub-systems in particular for wavelength division multiplexing (WDM) applications and ring resonator based applications. Developed in the course of PLAT4MFP7 European project, DAPHNE is a flexible platform that fits perfectly R&D needs. The fabrication flow enables the processing of photonic integrated circuits using a silicon-on-insulator (SOI) of 300nm, partial etches of 150nm and 50nm and a total silicon etching. Consequently, two varieties of rib waveguides and one strip waveguide can be fabricated simultaneously with auto-alignment properties. The process variability on the 150nm partially etched silicon and the thin 50nm slab region are both less than 6 nm. Using a variety of different implantation configurations and a back-end of line of 5 metal layers, active devices are fabricated both in germanium and silicon. An available far back-end of line process consists of making 20 μm diameter copper posts on top of the electrical pads so that an electronic integrated circuit can be bonded on top the photonic die by 3D integration. Besides having those fabrication process options, DAPHNE is equipped with a library of standard cells for optical routing and multiplexing. Moreover, typical Mach-Zehnder modulators based on silicon pn junctions are also available for optical signal modulation. To achieve signal detection, germanium photodetectors also exist as standard cells. The measured single-mode propagation losses are 3.5 dB/cm for strip, 3.7 dB/cm for deep-rib (50nm slab) and 1.4 dB/cm for standard rib (150nm slab) waveguides. Transition tapers between different waveguide structures are as low as 0.006 dB.

Characterization and Development of High Dose Implanted Resist Stripping Processes

With the increase of implantation dose in new technologies, implanted photoresist stripping is even more challenged in terms of efficiency and substrate consumption. In this work, the effect of implantation parameters (energy and implanted specie) on the photoresist modifications are studied and several plasma chemistries are evaluated to remove it. A good removal efficiency with a low substrate consumption has been found with H2-based processes especially N2H2.

Characterization of photoresist films exposed to high-dose implantation conditions

Alternative approaches are now required to fulfill the strict requirements of photoresist (PR) dry strip process after high-dose implantation. A better understanding of the PR degradations induced by the ion bombardment during the implantation is thus required. In this study, in-depth characterizations of PR films after arsenic and phosphorus-high-dose implantation have been made. The influence of the dopant species (As or P) as well as the implantation energy has been investigated. The experimental results have then been confronted to simulations performed with stopping and range of ions in matter (SRIM). The experimental results show the formation of a “crust layer” enriched in carbon and depleted in oxygen and hydrogen whose density, hardness, and elastic modulus are higher than the nonimplanted PR (pristine). SRIM simulations confirm that the PR degradation is mainly due to crosslinking phenomenon. Chemical analyses have revealed that the dopants are present in their elemental and oxidized forms in th...

Wet Process Developments for Electrical Properties Improvement Of 3D MIM Capacitors

3D architecture is an alternative way to high-k dielectric to increase the capacitance of MIM structure. However, the top of this kind of structure is very sensitive to defectivity and then requires a special wet treatment. In this paper, we present the process flow for a 3D MIM integration in a CMOS copper back-end and a two steps wet process which provides very good electrical performances, i.e. leakage current lower than 10-9A.cm-2 at 5V / 125°C and breakdown voltage higher than 20V. At first, a SC1 step is done for electrode isolation improvement by material etching with good selectivity towards dielectric: that’s the electrode recess. In the second time, a HF step is done for copper oxide dilution and residues removal from the top of the 3D structure.