C. Borowiak

Efficient multi-V T FDSOI technology with UTBOX for low power circuit design

For the first time, Multi-V<inf>T</inf> UTBOX-FDSOI technology for low power applications is demonstrated. We highlight the effectiveness of back biasing for short devices in order to achieve I<inf>ON</inf> current improvement by 45% for LVT options at an I<inf>OFF</inf> current of 23nA/µm and a leakage reduction by 2 decades for the HVT one. In addition, fully functional 0.299um² bitcells with 290mV SNM at 1.1V and Vb=0V operation were obtained. We also demonstrate on ring oscillators and 0.299µm² SRAM bitcells the effectiveness (ΔV<inf>T</inf> versus V<inf>b</inf> ∼ 208mV/V) of the conventional bulk reverse and forward back biasing approaches to manage the circuit static power and the dynamic performances.

Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology

In this paper, we present FD-SOI with High-K and Single Metal gate as a possible candidate for LP multimedia technology. Dual gate oxide co-integrated devices with EOT 17Å/Vdd 1.1V and 29Å/Vdd 1.8V are reported. The interest of Ultra-Thin Buried Oxide substrates (UTBOX) is reported in term of Multiple Vt achievement and matching improvement. Delay improvement up to 15% is reported on Ring Oscillators as compared to bulk 45nm devices. In addition, for the first time 99.998% 2Mbit 0.374µm2 SRAM cut functionality has been demonstrated. Thanks to a hybrid FDSOI/bulk co-integration with UTBOX all IPs required in a SOC are demonstrated for LP applications.

Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below

In this paper we explore for the first time the impact of an Ultra-Thin BOX (UTBOX) with and without Ground Plane (GP) on a 32nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50mV DIBL reduction by using 10nm BOX thickness for NMOS and PMOS devices at 33nm gate length. Moreover, the combination of DIBL reduction and threshold voltage modulation by adding GP enables to reduce the Isb current by a factor 2.8 on a 0.299µm2 SRAM cell while maintaining an SNM of 296mV @ Vdd 1.1V.

UTBOX and ground plane combined with Al 2 O 3 inserted in TiN gate for V T modulation in fully-depleted SOI CMOS transistors

Thin film devices (FDSOI) are among the most promising candidates for next device generations due to their better immunity to short channel effects (SCE). In addition, the introduction of high-k and metal gate has greatly improved the MOSFETs performance by reducing the electrical oxide thickness (CET) and gate leakage current. However, if midgap metal gate is sufficient to provide a high symmetrical threshold voltage (VT∼0.45V) for both NMOS and PMOS devices [1], still one major challenge is to provide VT modulation with an undoped channel in order to satisfy the low power (LP) circuit design requirements [2–5]. To overcome this issue, combining UTBOX substrate with ground plane (GP) has been proposed [2,5]. However this technique with midgap metal gate requires a FBB biasing in order to realize low VT thats implies a disruptive circuits design to avoid forward diode biasing in the substrate between the two opposite GP type beneath the BOX [6]. In order to introduce more VT modulation flexibilities and especially for LVT PMOS and HVT NMOS, aluminum Oxide (Al2O3) inserted in TiN gate stack has been proposed for bulk devices [7–8] in a gate first process. The viability of this option is studied in this paper for FDSOI, for HfO2 and HfSiON gate oxide, through transistors performance, reliability and variability analysis.

Hybrid Localized SOI/bulk technology for low power system-on-chip

This paper highlights the successful co-integration of Localized Silicon-On-Insulator (LSOI) devices and of bulk-Si I/O devices on the same chip. LSOI devices present good logic performances and very low mismatch values down to 1.2mV/µm. In addition, we show the backbiasing impact on LSOI SRAM bit-cells for stability improvement. This work also presents the co-integration of LSOI with bulk devices as a solution for the devices that are not compatible with thin-body technology. In particular, we demonstrate for the first time competitive bulk co-integrated ElectroStatic Discharge (ESD) protections.

A solution for an ideal planar multi-gates process for ultimate CMOS?

We demonstrate for the first time high-performant planar multi-gates devices with Si-conduction channel of 4nm, allowing drive current up to 1350µA/µm @Ioff=0.4nA/µm (Vdd=1.1V, CET=1.9nm). But as future multi-gates transistors need to have reduced capacitances and a simple robust process, we also demonstrate in this paper an ideal planar self-aligned solution, based on the direct exposure of a HSQ layer through a 5nm Si-channel. This opens the way to an easy planar multi-gate process for ultimate CMOS (11nm node & below), fully co-integrable with conventional devices.

Impact of 45° rotated substrate on UTBOX FDSOI high-k metal gate technology

All these results show mainly the effectiveness of 45° rotated substrate enabling an increase of mobility performance for PMOS as compared to not rotated substrate. For NMOS devices, combined access resistance and mobility improvements explain the performance gain for rotated substrate.

Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology

In this paper, we study how to boost the performance of FDSOI devices with High-K and Single Metal gate by using the combination of UTBOX GP and local back biasing integrated with our hybrid process. The interest of local back biasing is highlighted in term of V T modulation and power management study on the 45nm 0.374μm2 bitcells and on the ESD functionality as compared to bulk technology.

Localized SOI logic and bulk I/O devices co-integration for Low power System-on-Chip technology

The objective of this paper is to present the successful co-integration of Logic Ultra-Thin Body and Box (UTBB) devices and bulk-Si I/O devices on the same chip. The UTBB transistors are integrated locally on a Bulk wafer with the Localized Silicon On Insulator (LSOI) process technology with HfO2/TiN gate stack for low power applications. I/O co-integrated Bulk devices have a thicker interfacial SiO2 under the HfO2/TiN stack to be compatible with the I/O higher voltage. Both performances of logic UTBB and I/O bulk devices are presented.

Impact of substrate orientation on Ultra Thin BOX Fully Depleted SOI electrical performances

In this paper, we compare the electrical properties of Ultra Thin Buried Oxide (UTBOX) Fully Depleted Silicon On Insulator (FD-SOI) MOS devices for rotated and not rotated substrate with different gate lengths. We found a significant performance enhancement on FD-SOI PMOSFETs as expected, while keeping a good control of short channel effects. Surprisingly, to a lower extent, an improvement is also found for NMOS devices. We have also studied the carrier mobility degradation as a function of temperature and we point out the contribution of different mechanisms that reduce the mobility such as impurity Coulomb scattering, phonons and neutral defects as a function gate length. We find that there is no significant effect of rotated substrate on the mobility degradation. All these results are discussed and possible explanations are also given.