Simone Eminente

Understanding quasi-ballistic transport in nano-MOSFETs: part I-scattering in the channel and in the drain

In this paper, and in Part II, Monte Carlo (MC) simulations including quantum corrections to the potential and calibrated scattering models are used to study electronic transport in bulk and double-gate silicon-on-insulator MOSFETs with L/sub G/ down to 14-nm designed according to the 2003 International Technology Roadmap for Semiconductors. Simulations with and without scattering are used to assess the influence of quasi-ballistic transport on the MOSFET on-current. We analyze in detail the flux of back-scattered carriers. The role of scattering in different parts of the device is clarified and the MC results are compared to simple models for quasi-ballistic transport presented in the literature.

Understanding quasi-ballistic transport in nano-MOSFETs: part II-Technology scaling along the ITRS

The on-current and its ballistic limit for MOSFETs designed according to the 2003 International Technology Roadmap for Semiconductors down to the 45-nm node, are evaluated by using the full-band, self-consistent Monte Carlo simulator with quantum-mechanical corrections described in Part I. Our results show that quasi-ballistic transport increases for L/sub G/ below approximately 50 nm and contributes most part of the I/sub ON/ improvements related to scaling. Thanks to a lower vertical electric field, double-gate silicon-on-insulator MOSFETs with ultrathin body and low channel doping achieve performance closer to the ballistic limit than the bulk counterparts.

Enhanced ballisticity in nano-MOSFETs along the ITRS roadmap: a Monte Carlo study

In this work we have simulated the I/sub ON/ and its ballistic limit I/sub BL/ of MOSFETs designed according to the 2003 roadmap down to the 45 nm node, by using a full-band, self-consistent Monte Carlo simulator with quantum mechanical corrections. Our results show that scattering plays an important role by limiting the current for gate length down to at least 14 nm; the impact of quasi-ballistic transport increases for L/sub G/ below approximately 50 nm and contribute most part of the I/sub ON/ improvements related to scaling. Thanks to a lower transversal electric field, the DG SOI MOSFETs with low channel doping allow to get closer to the ballistic limit than bulk counterparts.

A Monte-Carlo study of the role of scattering in deca-nanometer MOSFETs

In this paper, a Monte-Carlo simulator, including quantum corrections to the potential and an improved physically based model for surface roughness scattering is used to study the electronic transport in double gate (DG) SOI MOSFETs with L/sub G/ down to 14nm. Our results demonstrate that, for the explored L/sub G/ values, scattering still controls the ON current (I/sub DS/), which for L/sub G/ = 25nm is overestimated by about a factor of 2 by a ballistic model. By monitoring the electrons back-scattered at the source, we discuss the role of the scattering in different parts of the device.

Small-Signal Analysis of Decananometer Bulk and SOI MOSFETs for Analog/Mixed-Signal and RF Applications Using the Time-Dependent Monte Carlo Approach

A state-of-the-art Monte Carlo simulator is applied to the investigation of the radio-frequency performance of bulk and ultrathin-body single-gate SOI MOSFETs that are designed according to the prescriptions of the 2005 ITRS for analog and mixed-signal applications. We provide an analysis of the signal-delay buildup along the channel and an investigation of the scaling properties of the parameters of the ac equivalent circuit, the transition frequency, and the 3-dB bandwidth of the voltage gain in common-source configuration. A comparison with a standard drift-diffusion approach is presented in order to discuss the main differences between the two transport models in terms of high-frequency ac analysis.

Monte Carlo Simulation of deca-nanometer MOSFETs for Analog/Mixed-signal and RF applications

A state of the art Monte-Carlo simulator is applied to the investigation of the RF performance of bulk MOSFETs designed according to the prescriptions of the 2005 ITRS Roadmap for analog and mixed signal applications, and of a 53 nm ultra-thin-body (UTB) single-gate (SG) SOI MOSFET. We provide an analysis of the signal-delay build-up along the channel and an investigation of the scaling properties of the parameters of the AC equivalent circuit, the transition frequency FT, and the 3dB bandwidth of the voltage gain in common-source configuration. The effects of ballistic transport and their impact on the AC figures of merit are investigated for short UTB double-gate MOSFETs