Climbing Huang

A comprehensive process engineering on TDDB for direct polishing ultra-low k dielectric Cu interconnects at 40nm technology node and beyond

The failure ratios of the three typical time-dependent dielectric breakdown (TDDB) failure modes, including top interface, sidewall and bottom corner areas, have been identified for a direct polishing ultra low k (ULK) dielectric Cu back-end-of-line (BEOL) structure at 40nm node. The Cu surface roughness of the metal lines, and the adhesion and thickness of the metal capping layers are strongly correlated to the top interface failure mode. The dielectric constant of the ULK and the concentration of the aluminum-doped Cu (CuAl) seed layer could be related to the sidewall failure mode. The bottom corner failures are induced by inappropriate Cu barrier re-sputter processes. In this study, the TDDB reliability performance can be effectively improved by evaluating a post-Cu chemical mechanical polishing (Cu CMP) cleaning process with smooth Cu surface roughness, developing a better step coverage with multi-layer capping layer, using a slightly higher dielectric constant ULK film, replacing a conventional pure Cu with a CuAl seed layer and optimizing the Cu barrier layer deposition process. The lifetime of the TDDB can be significantly improved over three orders (larger than 10000 years) as implementing an optimized integrated Cu with ULK BEOL structures at 40nm technology node.

Effects of BEOL copper CMP process on TDDB for direct polishing ultra-low k dielectric cu interconnects at 28nm technology node and beyond

A robust Cu chemical mechanical polishing (CMP) process with better post CMP polishing profile, range, lower defectivity, smooth copper surface, tighten metal line sheet resistance (Rs) and pattern loading control has been evaluated during the Cu-CMP process at 28nm and beyond. Various reasons of Time-Dependent Dielectric Breakdown (TDDB) failure including micro-scratches on interconnect surface post Cu CMP, new barrier slurry with lower solid content, smaller abrasive size and polish pad with lower hardness than Dow pad IC pad from a direct polishing ultra low k (ULK) dielectric Cu back-end-of-line (BEOL) structure at 28nm node and beyond will be discussed. It is clearly shown that with smaller slurry abrasive and lower content ratio, TDDB performance can be improved. Furthermore, based on this study, the TDDB reliability performance also can be effectively improved by using a new barrier slurry with better copper recess and pattern density loading control, soft polish pad with smooth Cu surface, a better step coverage with multi-layer capping layer, and a slightly higher dielectric constant ULK film. The lifetime of the TDDB can be significantly improved over two orders of magnitudes by implementing an optimized new barrier slurry and softer polish pad at 28nm technology node.

Fast and accurate scatterometry metrology method for STI CMP step height process evaluation

At the 28nm node using 300mm wafers, oxide step height in STI CMP transient gate after-etch inspection (TG AEI) wafers is a critical parameter that affects device performance and should be monitored and controlled. For production process control of this kind of structure, a metrology tool must utilize a non-destructive measurement technique, and have high sensitivity, precision and throughput [1]. This paper discusses a scatterometry-based measurement method for monitoring critical dimension step height in STI CMP instead of traditional measurement methods such as atomic force microscopy (AFM). The scatterometry tool we used for our investigations was the KLA-Tencor SpectraShape 8810, which is the most recent model of the spectroscopic critical dimension (SCD) metrology tools that have been implemented in production for process control of TG AEI structures. AFM was used as a reference metrology technique to assess the accuracy performance of the SpectraShape8810. The first objective of this paper is to discuss the best azimuth angle and floating parameters for scatterometry measurement of the step height feature in TG AEI wafers. Second, this paper describes the tool matching performance of SpectraShape 8810 and correlation to AFM determined using a DOE of TG AEI wafers.

The TDDB failure mode and its engineering study for 45nm and beyond in porous low k dielectrics direct polish scheme

To keep pursuing the chip resistance capacitance (RC) delay improvement, it is necessary to further reduce k value. Accordingly, direct polished porous type ultra-low-k (ULK) film instead of non-porous low-k materials is integrated into Cu interconnects from 45 nm. However, because of the ULK characteristics and the minimized feature size, the time-to-break-down (TDDB) failure mode behaves different from silica glass or nonporous low-k film. And it is not only sensitive to geometries but also very sensitive to the engineering in the fabrication process. In this paper, we identified three TDDB failure modes, Cu protrusion from trench top interface, sidewall, and bottom corner, in the direct polished ULK scheme. In addition, on the basis of those failure modes, the related mechanisms in conjunction with the sensitivity to the processes are reported as well.

Chemical and Plasma Oxidation Behaviors of NiSi and NiPtSi Salicide Films in 65nm Node CMOS Process

The chemical and plasma oxidation behaviors of NiSi and NiPtSi salicide films in a 65 nm node CMOS device fabrication process have been investigated. By incorporating Pt into the nickel salicide formation process, the oxidation rate can be effectively reduced during both salicidation etch/clean and contact plasma etch processes. Data collected from this study suggests both stronger chemical bonding from PtSi and the aggregation of Pt near film surface attribute to this good oxidation resistance property.

Formation of Ni(Pt) Germanosilicide Using a Sacrificial Si Cap Layer

Ni(Pt) alloy has been implemented in the SiGe silicidation process for 65nm node CMOS device fabrication. A thin Si cap layer was introduced into the in-situ doped Si1-xGexB film stack to further enhance the thermal stability of the silicide film. The Ni(Pt) germanosilicide temperature transition curves have been studied, N-/P-FET mismatch issues have been resolved, and a robust integration flow has been developed for the 65 nm node CMOS device fabrication.

Defect study of manufacturing feasible porous low k dielectrics direct polish for 45nm technology and beyond

In this paper, the specific 45nm direct polish related defects and its effects were investigated in order to achieve the high yield manufacturing feasibility of direct polish to porous low-k dielectric film. Crater defect (ring shape metal bridge) was identified caused by abrasive residue in the pre-metal layer polish. Polished with colloidal silica based Cu slurry could suppress this defect efficiently. The plasma treatment on porous ultra low-k (ULK) layer improved the adhesion. However, it induced peeling when polish stop at this treated interface. It could be removed if further polish to intact ULK film. High Cu roughness possibly induced both pattern missing and via open in the following metal layer and suffered the yields. The V1M2 upstream electro-migration (EM) at this generation highly correlated to the roughness degree. By optimizing clean chemical concentration and clean time satisfied the needs of Cu roughness. Yield improvement proved the manufacturing feasibility of ULK direct polish technology.

Micro-scratch reduction of replacement metal gate aluminum chemical mechanical polishing at 28nm technology node

The defectivity control of replacement metal gate (RMG) chemical mechanical polishing was important for high-k metal gate (HKMG) process. Micro-scratches of RMG CMP easily caused shorting or open of devices. In this study, the micro-scratch reduction of aluminum chemical mechanical polishing (AlCMP) has been investigated to provide solutions for preventing the formation of micro-scratches. Micro-scratches can be reduced by implementing soft pads at platen 2 and platen 3, pad cleaning chemical, and optimized post cleaning condition. Soft pads can reduce micro-scratch levels of AlCMP process, especially at platen 2. However, AlCMP with soft pads easily suffer serious dishing or erosion. Therefore, the balance between micro-scratches and dishing or erosion was crucial for pad selection of AlCMP. Besides, removal of pad stain was also important. Pad stain removed by pad cleaning chemical could get a lower micro-scratch level of AlCMP. In addition to polishing process, post cleaning process was a source of micro-scratch for AlCMP. An unsuitable post cleaning condition caused a counter effect of micro-scratch reduction.

A novel pre-clean process of BEOL barrier-seed process to enhance reliability performance of advanced 40nm node

With scaling down of device geometry and keeping improvement of the chip resistance capacitance (RC) delay, it is necessary to reduce k value. A porous ultra low k-value (ULK) dielectric film is integrated into Cu interconnects of advanced 40 nm. There are several papers discussing about the interface effect between ULK film and barrier on reliability performance [1][2]. This paper will discuss the effect of pre-clean process on reliability performance before barrier and Cu-seed layer deposition that will strong affect the interface properties. Also, the early failure mode of each pre-clean process will be discussed as well to clarify the proposed mechanism.

A model for post-CMP cleaning effect on TDDB

For 45 nm and beyond, direct polished porous type ultra low-K film (ULK) is integrated in Cu interconnects. Post-cleaning of Cu CMP effect on Time dependent dielectric breakdown (TDDB) was investigated. Cu ions remaining on dielectrics and Cu roughness are found as two dominate factors at different clean time region. High Cu roughness induced capping layer seam results in the degradation of TDDB. A statistical model, said weak element model, was proposed to illustrate the correlation of Cu roughness on TDDB as well.