Ko-Min Chang

Silicon nanocrystal non-volatile memory for embedded memory scaling

In this paper, we present key features of silicon nanocrystal memory technology. This technology is an attractive candidate for scaling of embedded non-volatile memory (NVM). By replacing a continuous floating gate by electrically isolated silicon nanocrystals embedded in an oxide, this technology mitigates the vulnerability of charge loss through tunnel oxide defects and hence permits tunnel oxide and operating voltage scaling along with accompanied process simplifications. However, going to discrete nanocrystals brings new physical attributes that include the impact of Coulomb blockade or charge confinement, science of formation of nanocrystals of correct size and density and the role of fluctuations, all of which are addressed in this paper using single memory cell and memory array data.

Study of single silicon quantum dots' band gap and single-electron charging energies by room temperature scanning tunneling microscopy.

Scanning tunneling spectroscopy in the shell-filling regime was carried out at room temperature to investigate the size dependence of the band gap and single-electron charging energy of single Si quantum dots (QDs). The results are compared with model calculation. A 12-fold multiple staircase structure was observed for a QD of about 4.3 nm diameter, reflecting the degeneracy of the first energy level, as expected from theoretical calculations. The systematic broadening of the tunneling spectroscopy peaks with decreasing dot diameter is attributed to the reduced barrier height for smaller dot sizes and to the splitting of the first energy level.

Embedded split-gate flash memory with silicon nanocrystals for 90nm and beyond

We present a split-gate based NOR flash memory array with silicon nanocrystals as the storage medium. 128 KB memory arrays have been evaluated with this technology and the results presented here show a nanocrystal memory that has been demonstrated to achieve a minimum 1.5 V operating window that is maintained through 10 K program/erase cycles; well controlled array threshold distributions; fast source-side injection programming (10-20 us); fast tunnel erase into the gate; and robust high temperature data retention for both uncycled and cycled arrays. Results presented here with focus on the array operation demonstrate the maturity of this technology for implementation into consumer, industrial, and automotive microcontrollers.

A 90nm Embedded 2-Bit Per Cell Nanocrystal Flash EEPROM

A two bit/cell embedded nanocrystal bitcell with low write current SSI program and tunnel erase in which nanocrystals are located under dedicated control gates has been demonstrated. Write bias conditions which mitigate gate disturb in a top erase capable bitcell have been confirmed

An advanced embedded flash technology for broad market applications

In June 2010, Freescale introduced the Kinetis product family of ARM®-core based 32-bit microcontrollers (MCUs) built on the 90nm TFS (Thin Film Storage) embedded flash technology. That was the first time a flash technology based on the silicon nanocrystals as the storage medium was ever productized - fully 14 years after Tiwari introduced the concept of nanocrystal memory [1]. This paper describes the TFS technology, the architecture, the special features, the robustness, and the extendibility to 40nm and beyond.