Yann Deval

Distributed MOS varactor biasing for VCO gain equalization in 0.13 /spl mu/m CMOS technology

The paper describes work done on a LC-VCO to linearize its frequency-voltage (Kvco) characteristic in order to extend its versatility. The technology used is a standard 0.13 /spl mu/m CMOS supplied by 1.2 V. The optimization is made on the varactor stage of the resonator and gives a nearly constant Kvco (140/spl plusmn/10 MHz/V from 2.36 GHz to 2.44 GHz), in spite of the MOS varactor non-linear characteristic, with still a good pushing (9 MHz/V) and constant phase noise (-126 dBc/Hz at 3 MHz offset).

Design of a 0.9 V 2.45 GHz Self-Testable and Reliability-Enhanced CMOS LNA

A self-testable and highly reliable low noise amplifier designed in 0.13 m CMOS technology is presented in this paper. This reliable LNA could be used to design the front-end of critical nodes in wireless local area networks to ensure data transmission. The LNA test, based on a built-in self test methodology, monitors its behavior. The test circuit is composed of one sensor and one biasing voltage sensor, and it offers high fault coverage. The high reliability is ensured by the use of redundancies. The LNA works under a 0.9 V supply voltage and the test chip has RF characteristics suitable for 802.11b/g applications. Parametric faults are injected and detected to demonstrate the efficiency of the BIST circuitry. Thanks to the switching on redundant blocks, performances are maintained and hence this proves the reliability of the methodology proposed.

Investigation of single-event transients in voltage-controlled oscillators

The responses of voltage-controlled oscillators (VCOs) to single-event transients (SETs) are investigated. Laser testing and simulations indicate that ion strikes on critical transistors cause distortions in the oscillating output. The time it takes for the circuit to resume its normal operating condition is limited by the recovery time of the affected transistor(s) and the oscillator startup time. These limits to circuit recovery time are the primary causes of the frequency dependence of SET responses in VCOs.

A reconfigurable RF power amplifier biasing scheme

A reconfigurable power amplifier (PA) is studied in this paper, dedicated to multi-mode, multi-standard radio frequency front-end (RFFE), from a low cost approach. The reconfigurable amplifier topology is presented, made up of two-stages independently controllable by the biasing scheme proposed which allows the dynamic modification of the quiescent current of the RF transistor, to adapt both its linearity and its output power in order to fulfill different standards specifications.

A 60µW LNA for 2.4 GHz wireless sensors network applications

This work reports on the implementation of a 2.4 GHz ultra low power (ULP) low noise amplifier (LNA) in a standard CMOS 0.13 µm process. The proposed design methodology consists in optimizing the tradeoff between RF performances and current consumption of the MOS transistor. The supply of the circuit controlled by a 3bits DAC varies from 0.4 to 0.6 V. This digital tuning allows maximizing the figure of merit of the LNA. The approach yields the operating point within the sweet spot region of the amplifying transistors. Experimental results of the circuit indicate a power dissipation of 60 µW@0.4V, a noise figure of 5.3 dB, and a forward gain of 13.1 dB. The IIP3 and ICP1 are −12 dBm and −19 dBm, respectively. This works aims the development of a complete RF front end for micro-watt radio.

HiperLAN 5.4-GHz low-power CMOS synchronous oscillator

A 5.4 GHz 0.25 /spl mu/m VLSI CMOS synchronous oscillator is proposed, which is designed to act as a local oscillator for HiperLAN systems. The design strategy is described, including the synchronization range optimization approach. A chip is presented, which provides a 150 MHz synchronization range and a -97 dBc/Hz phase noise at 10 kHz offset from the carrier, while only consuming 5 mA from a 2.5 V supply.

A Disruptive Receiver Architecture Dedicated to Software-Defined Radio

The next generation of mobile terminals is faced with the emergence of the software-defined radio (SDR) concept. The communication devices tend to provide various wireless services through a multi-functional, multi-mode and multi-standard terminal. The SDR concept aims at designing a re-configurable radio architecture accepting all cellular or noncellular standards working in the 0-5-GHz frequency range. Some technical challenges have to be solved in order to address this concept. Working in the digital domain may be a solution but the analog-to-digital conversion cannot be done at Radio Frequencies, at an acceptable resolution and at an acceptable level of power consumption. The idea proposed here was to interface an analog pre-processing circuit between the antenna and a digital signal processor to pre-condition the RF signal. It uses the principle of a fast Fourier transform to carry out basic functions with high accuracy in a low-cost technology like CMOS. This paper presents the design and the behavioral simulations of this analog discrete-time device which gives the hardware flexibility required for a cognitive radio component.

The Experimental Demonstration of a SASP-Based Full Software Radio Receiver

Many technological bottlenecks prevent from realizing a software radio (SR) mobile terminal. The old way of building radio architectures is now over because a single handled terminal has to address various communication standards. This paper exposes a SR receiver: a sampled analog signal processor (SASP) is designed to perform downconversion and channel presorting. The idea is to process analog voltage samples in order to recover in baseband any RF signal emitted from 0 to 5 GHz. An analog fast Fourier transform achieves both frequency shifting and filtering. An experimental demonstrator of the SASP using 65 nm CMOS technology from STMicroelectronics is here presented and measured. It validates the concept of a new SR receiver with the design of a demonstrator which runs at 1.2 GHz consuming 389 mW.

SPICE modeling of the transient response of irradiated MOSFETs

A new SPICE model of irradiated MOSFET taking into account the real response of the four electrodes is proposed. A comparison between SPICE-generated transient response and PISCES device simulation demonstrates the accuracy benefits when used in complex electronic architectures.

A Disruptive Software-Defined Radio Receiver Architecture Based on Sampled Analog Signal Processing

Software defined radio (SDR) aims at bringing digital treatment chip closer to the antenna in a mobile terminal architecture. The main goal is to create a re-configurable radio architecture accepting all the cellular or non-cellular standards working in the 0-5 GHz frequency range. But, in this environment, the analog to digital conversion and the digital operations face issues like power supply and processing speed. The idea is to interface a preprocessing circuit between the antenna and a digital signal processor (DSP) to pre-condition the RF signal. This paper presents the design of an analog discrete-time device located between antenna and a DSP in standard radio architecture. It uses the principle of the discrete Fourier transform (DFT) to reduce the frequency of the DSP-input-signal treatment to fulfil the SDR purpose. It has been validated through system level simulation.