Louis C. Parrillo

The effects of boron penetration on p/sup +/ polysilicon gated PMOS devices

The penetration of boron into and through the gate oxides of PMOS devices which employ p/sup +/ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V/sub FB/, increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF/sub 2/ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi/sub 2/ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO/sub 2//Si interface. >

The influence of fluorine on threshold voltage instabilities in p/sup +/ polysilicon gated p-channel MOSFETs

It is shown that fluorine plays a major role in the penetration of boron into and through the gate oxides of p-channel MOSFETs that use p/sup +/ doped polysilicon gates. Boron penetration results in large positive shifts in V/sub FB/, increased p-channel subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Inclusion of a phosphorus coimplant or TiSi/sub 2/ salicide is shown to minimize this effect. The boron penetration phenomenon is modeled by the creation of a very shallow, fully depleted p-type layer in the silicon substrate close to the SiO/sub 2/-Si interface. Elemental boron is shown to be superior to BF/sub 2/ as an implant species for surface channel submicron PMOS devices.<<ETX>>

A physical model for boron penetration through thin gate oxides from p/sup +/ polysilicon gates

Based on numerical device and process simulation, it is shown that enhancement of the boron diffusivity by as much as 300 times in the thin gate oxide results in a very shallow exponential p-type profile in the underlying silicon substrate. The effect of fluorine and phosphorus coimplantation into the p-type polysilicon gate is modeled by changes in the boron diffusivity in the gate oxide and segregation at the polysilicon-oxide interface. An inverse PMOS short-channel behavior in which the threshold voltage becomes more negative with decreasing channel length is modeled by two-dimensional boron segregation effects caused by the poly gate oxidation.<<ETX>>

Poly-gate sidewall oxidation induced submicrometer MOSFET degradation

The effect of poly-gate sidewall oxidation on short-channel MOSFET behavior is examined. The gain, threshold voltage, and apparent electrical channel length are shown to be very sensitive to the location of the n/sup -/ junction edge with respect to the poly-gate edge for a lightly-doped-drain NMOS transistor. New guidelines for the design of submicrometer MOSFETs based on an analysis of the sidewall oxidation of the polysilicon after gate definition are proposed.<<ETX>>

A scalable submicron contact technology using conformal LPCVD TiN

A scalable submicron contact technology has been developed using a fully conformal LPCVD (low-pressure chemical vapor deposition) titanium nitride barrier metal that provides low contact resistance to salicide, low leakage, excellent adhesion, and high thermal stability. Owing to the uniform step coverage, especially in deep, straight wall contacts, the CVD TiN overcomes the metal reliability and junction leakage issues associated with the physical sputtering of metals in high-aspect-ratio, submicron contacts. LPCVD TiN withstands 550 degrees C thermal stress, maintaining low contact resistance and leakage, while physically deposited TiN fails at 500 degrees C. The applicability of CVD TiN barrier technology to VLSI devices has been successfully demonstrated on production circuits.<<ETX>>

A high-performance sub-half micron CMOS technology for fast SRAMs

An advanced high-performance sub-half-micron technology for fast CMOS SRAMs (static RAMs) has been developed. Features of this thin-well process include: an aggressive interwell isolation module, framed-mask poly-buffered LOCOS isolation (FMPBL), a 125-AA gate oxide, dual n/sup +//p/sup +/ implanted polysilicon gates, titanium salicide, two levels of polysilicon, TiN metallization barriers, a poly plug option, and up to three layers of metallization. An interwell isolation process allows scaling of the n/sup +/ to p/sup +/ space to less than 2 mu m. Active transistor design is optimized to reduce the polysilicon gate birds beak and LDD (lightly doped drain) underdiffusion. Discrete transistor lifetimes for hot carrier degradation are in excess of 10 years of 3.3-V operation. A 16 K*4 SRAM displays no parametric shifts after HCl stressing for 1000 h at 7 V and 0 degrees C. Ring oscillator delay times of 85 ps at 3.3-V and 65 ps at 5-V supply are obtained.<<ETX>>

A high-performance half-micrometer generation CMOS technology for fast SRAMs

An advanced, high-performance, half-micrometer generation technology has been developed for fast CMOS SRAM circuits. This process features an aggressive interwell isolation module which allows scaling of the n/sup +/ to p/sup +/ space to less than 2 mu m and an advanced framed-mask poly-buffered LOCOS isolation (FMPBL) which reduces field oxide encroachment and the transistor narrow-width effect and provides a 1.2- mu m active pitch. Transistors are fabricated with a 125-A gate oxide and a dual n/sup +//p/sup +/ source/drain implanted polysilicon gates to provide excellent short-channel behavior down to 0.3- mu m effective channel length. Transistor design is optimized to reduce the polysilicon gate birds beak and lightly doped drain (LDD) underdiffusion. For PMOS transistors, boron diffusion through the gate oxide is minimized by replacing BF/sub 2/ with B/sup 11/ for the p/sup +/ S/D implant. A titanium salicide process provides strapping between n/sup +//p/sup +/ polysilicon gates and lower sheet and contact resistances. The back-end features three levels of metallization and polysilicon contact plugs. Discrete transistor lifetimes for DC hot-carrier degradation are in excess of 10 years at 3.3-V operation. A 16 K* 4 SRAM displayed no parametric shifts after hot-carrier stressing for 1000 h at 7-V and 0 degrees C. This is consistent with a lifetime of greater than 10 years at 3.3-V operation. Ring oscillator delay times of 85 ps at 3.3-V and 65 ps at 5-V supply are achieved. >

Disposable polysilicon LDD spacer technology

An advanced 0.5- mu m CMOS disposable lightly doped drain (LDD) spacer technology has been developed. This 0.5- mu m CMOS technology features surface-channel LDD NMOS and PMOS devices, n/sup +//p/sup +/ poly gates, 125-A-thick gate oxide, and Ti-salicided source/drain/gate regions. Using only two masking steps, the NMOS and PMOS LDD spacers are defined separately to provide deep arsenic n/sup +/ regions for lower salicided junction leakage, while simultaneously providing shallow phosphorus n/sup -/ and boron p/sup -/ regions for improved device short-channel effects. Additionally, the process allows independent adjustment of the LDD and salicide spacers to optimize the LDD design while avoiding salicide bridging of source/drain to gate regions. The results indicate extrapolated DC hot-carrier lifetimes in excess of 10 years for a 0.3- mu m electrical channel-length NMOS device operated at a power-supply voltage of 3.3 V. >

Substrate bias dependent leakage in LDD MOSFETs

A new leakage mechanism that is a strong function of substrate bias has been observed on lightly doped drain (LDD) MOSFETs. The substrate bias dependence on this drain-to-substrate leakage current is shown to be related to the formation of sidewall spacers. Devices with a conventional oxide spacer exhibit substrate-bias-dependent leakage with a wide variation in leakage characteristics. Devices with a disposable spacer, however, do not exhibit such leakage and have a small variation in leakage characteristics. The deleterious leakage characteristics observed with conventional oxide spacers are caused by defects produced in the silicon along the spacer edge during spacer formation. These defects can be avoided with a spacer formation process that does not etch into silicon in the source/drain regions.<<ETX>>

An integrated 0.5 mu m CMOS disposable TiN LDD/salicide spacer technology

A novel disposable TiN LDD/salicide spacer process has been developed for a 0.5- mu m CMOS technology. Both LDD (lightly doped drain) and salicide definition are obtained using a single disposable TiN spacer. This process results in CMOS devices with low salicided junction leakage, reduced source/drain lateral diffusion, and shallow phosphorus n- and boron p-regions for improved short-channel behavior.<<ETX>>