Richard D. Sivan

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior.<<ETX>>

A self-aligned LDD/channel implanted ITLDD process with selectively-deposited poly gates for CMOS VLSI

A novel inverse-T LDD (ITLDD) CMOS process has been developed as part of a submicron CMOS technology that features self-aligned LDD/channel implantation for improved hot-carrier protection. The resulting ITLDD device structures can be designed with very light n- and p-LDD (lightly doped drain) implantations. This leads to lower substrate current due to reduced compensation effects of the lightly doped LDD regions by the heavy channel doping profile. The use of selective polysilicon deposition rather than an incomplete polysilicon etchback process to define the inverse-T gate results in a simpler, more manufacturable process for the ITLDD structure.<<ETX>>

A high-performance half-micrometer generation CMOS technology for fast SRAMs

An advanced, high-performance, half-micrometer generation technology has been developed for fast CMOS SRAM circuits. This process features an aggressive interwell isolation module which allows scaling of the n/sup +/ to p/sup +/ space to less than 2 mu m and an advanced framed-mask poly-buffered LOCOS isolation (FMPBL) which reduces field oxide encroachment and the transistor narrow-width effect and provides a 1.2- mu m active pitch. Transistors are fabricated with a 125-A gate oxide and a dual n/sup +//p/sup +/ source/drain implanted polysilicon gates to provide excellent short-channel behavior down to 0.3- mu m effective channel length. Transistor design is optimized to reduce the polysilicon gate birds beak and lightly doped drain (LDD) underdiffusion. For PMOS transistors, boron diffusion through the gate oxide is minimized by replacing BF/sub 2/ with B/sup 11/ for the p/sup +/ S/D implant. A titanium salicide process provides strapping between n/sup +//p/sup +/ polysilicon gates and lower sheet and contact resistances. The back-end features three levels of metallization and polysilicon contact plugs. Discrete transistor lifetimes for DC hot-carrier degradation are in excess of 10 years at 3.3-V operation. A 16 K* 4 SRAM displayed no parametric shifts after hot-carrier stressing for 1000 h at 7-V and 0 degrees C. This is consistent with a lifetime of greater than 10 years at 3.3-V operation. Ring oscillator delay times of 85 ps at 3.3-V and 65 ps at 5-V supply are achieved. >

Disposable polysilicon LDD spacer technology

An advanced 0.5- mu m CMOS disposable lightly doped drain (LDD) spacer technology has been developed. This 0.5- mu m CMOS technology features surface-channel LDD NMOS and PMOS devices, n/sup +//p/sup +/ poly gates, 125-A-thick gate oxide, and Ti-salicided source/drain/gate regions. Using only two masking steps, the NMOS and PMOS LDD spacers are defined separately to provide deep arsenic n/sup +/ regions for lower salicided junction leakage, while simultaneously providing shallow phosphorus n/sup -/ and boron p/sup -/ regions for improved device short-channel effects. Additionally, the process allows independent adjustment of the LDD and salicide spacers to optimize the LDD design while avoiding salicide bridging of source/drain to gate regions. The results indicate extrapolated DC hot-carrier lifetimes in excess of 10 years for a 0.3- mu m electrical channel-length NMOS device operated at a power-supply voltage of 3.3 V. >

An ITLDD CMOS process with self-aligned reverse-sequence LDD/channel implantation

An advanced inverse-T LDD (ITLDD) CMOS process has been developed. This process features self-aligned lightly-doped-drain/channel implantation for improved hot-carrier protection. Selective polysilicon deposition is used to define the thick polysilicon gate regions with a thin polysilicon gate regions overlying the lightly doped n/sup -/ and p/sup +/ regions. Since the thick poly gate regions are defined by nitride sidewall spacers, optical lithography can be used to define sub-half-micrometer gate length MOSFETs. The LDD implants are performed after the n/sup +/ and p/sup +/ implants are annealed, resulting in MOSFETs with improved short-channel behavior due to the smaller lateral source/drain diffusion. >

A selectively deposited poly-gate ITLDD process with self-aligned LDD/channel implantation

An inverse-T lightly doped drain (ITLDD) CMOS process which features improved hot-carrier effects and self-aligned source/drain and channel implantation profiles is presented. Compensation effects by the heavy channel doping on the light N/sup -//P/sup -/ profile are minimized in this ITLDD structure, because the implants are self-aligned to the polysilicon-gate edge. In addition, because selective polysilicon deposition rather than an incomplete poly-gate etchback is used to define the ITLDD structure, a simpler, more manufacturable process is obtained due to improved control of the thin poly-gate shelf thickness.<<ETX>>