Craig S. Lage

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor, Vdd can be further scaled to 1.0 V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at Lgate = 30 nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.

Soft error rate and stored charge requirements in advanced high-density SRAMs

This work presents a quantitative model which attributes most soft errors in dense SRAMs not to alpha particles as is commonly accepted, but to cosmic ray events. This work also elucidates for the first time the stored charge required in SRAM cells to achieve acceptable soft error rates. Enhancements to add capacitance are necessary at the 4 Megabit level and beyond. One method of enhancing the cell capacitance is reported in detail.<<ETX>>

Another shock for the Bullet cluster, and the source of seed electrons for radio relics

ABSTRACT With Australia Telescope Compact Array observations, we detect a highly elongatedMpc-scale diffuse radio source on the eastern periphery of the Bullet cluster 1E0657-55.8,which we argue has the positional, spectral and polarimetric characteristics of a radio relic.This powerful relic (2:3 0:1 10 25 WHz 1 ) consists of a bright northern bulb and a faintlinear tail. The bulb emits 94% of the observed radio flux and has the highest surface bright-ness of any known relic. Exactly coincident with the linear tail we find a sharp X-ray surfacebrightness edge in the deep Chandra image of the cluster – a signature of a shock front inthe hot intracluster medium (ICM), located on the opposite side of the cluster to the famousbow shock. This new example of an X-ray shock coincident with a relic further supports thehypothesis that shocks in the outer regions of clusters can form relics via diffusive shock (re-)acceleration. Intriguingly, our new relic suggests that seed electrons for reacceleration arecoming from a local remnant of a radio galaxy, which we are lucky to catch before its com-plete disruption. If this scenario, in which a relic forms when a shock crosses a well-definedregion of the ICM polluted with aged relativistic plasma – as opposed to the usual assumptionthat seeds are uniformly mixed in the ICM – is also the case for other relics, this may explaina number of peculiar properties of peripheral relics.Key words: radiation mechanisms: non-thermal – acceleration of particles – shock waves –galaxies: clusters: individual: 1E 0657-55.8 – galaxies: clusters: intracluster medium – radiocontinuum general

Soft-error-rate improvement in advanced BiCMOS SRAMs

An improvement in soft-error-rate (SER) achieved by implementing a triple-well structure in a BiCMOS process is discussed. For 4-Mb SRAMs fabricated in a BiCMOS process, an optimized triple-well process improves the accelerated SER (ASER) by over two orders of magnitude without compromising device performance. Diode charge collection and ASER measurements show excellent correlation across several BiCMOS and CMOS processes.<<ETX>>

Scaling of 32nm low power SRAM with high-K metal gate

This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum2 and 0.124 mum2. SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG Tinv scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact process. A dual-ground write assist option can additionally enable ultra dense 0.124 mum2 cell to meet low power application requirements.

Deep radio observations of the radio halo of the bullet cluster 1E 0657−55.8

We present deep 1.1-3.1 GHz Australia Telescope Compact Array observations of the radio halo of the bullet cluster, 1E 0657-55.8. In comparison to existing images of this radio halo the detection in our images is at higher significance. The radio halo is as extended as the X-ray emission in the direction of cluster merger but is significantly less extended than the X-ray emission in the perpendicular direction. At low significance we detect a faint second peak in the radio halo close to the X-ray centroid of the smaller sub-cluster (the bullet) suggesting that, similarly to the X-ray emission, the radio halo may consist of two components. Finally, we find that the distinctive shape of the western edge of the radio halo traces out the X-ray detected bow shock. The radio halo morphology and the lack of strong point-to-point correlations between radio, X-ray and weak-lensing properties suggests that the radio halo is still being formed. The colocation of the X-ray shock with a distinctive radio brightness edge illustrates that the shock is influencing the structure of the radio halo. These observations support the theory that shocks and turbulence influence the formation and evolution of radio halo synchrotron emission.

Device drive current degradation observed with retrograde channel profiles

Super steep retrograde channel profiles have been widely known to produce improved short channel characteristics in sub-0.35 /spl mu/m CMOS technologies. In this paper, an attempt is made to leverage this improved short channel behaviour and thereby improve transistor performance (as measured by the current drive). Whereas significant improvements in short channel effects measured by DIBL and /spl Delta/Vt/sub sat/ are obtained with retrograde channels, it is observed that for a fixed gate length and equal threshold voltage, transistors with retrograde channel profiles typically exhibit lower drive currents than equivalent transistors fabricated with conventional doping profiles. Potential trade offs in device design resulting from this observation are discussed.

A high-performance 0.5- mu m BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5- mu m BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 mu m/sup 2/ by creating self-aligned bit-sense and V/sub ss/ contacts. A WSi/sub x/ polycide emitter n-p-n transistor with an emitter area of 0.8*2.4 mu m/sup 2/ provides a peak cutoff frequency (f/sub T/) of 14 GHz with a collector-emitter breakdown voltage (BV/sub CFO/) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f/sub T/ and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process. >

Advanced SRAM technology-the race between 4T and 6T cells

This work discusses the trade-offs between 4T SRAM cells which use four bulk transistors (and have poly resistor or TFT loads) and 6T SRAM cells which use six bulk transistors (and use bulk PMOS loads). 4T SRAM cells have dominated the stand-alone SRAM market since first introduced in the 1970s, but 6T SRAM cells have been dominant for on-chip storage in advanced microprocessors and other logic circuits. However, recently there has been a resurgence of interest in 6T cells for stand alone SRAM applications. While 4T cells are typically smaller, they generally require a more complex process, and have poorer stability, especially at low voltage. This paper quantitatively examines several different trade-offs in SRAM cell design.

A quadruple well, quadruple polysilicon BiCMOS process for fast 16 Mb SRAM's

An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 /spl mu/m/sup 2/ with conventional I-line lithography and 7.32 /spl mu/m/sup 2/ with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a 1.0 /spl mu/m active pitch, MOSFET transistors designed for a 0.80 /spl mu/m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance. >