Thomas C. Mele

The effects of boron penetration on p/sup +/ polysilicon gated PMOS devices

The penetration of boron into and through the gate oxides of PMOS devices which employ p/sup +/ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V/sub FB/, increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF/sub 2/ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi/sub 2/ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO/sub 2//Si interface. >

The influence of fluorine on threshold voltage instabilities in p/sup +/ polysilicon gated p-channel MOSFETs

It is shown that fluorine plays a major role in the penetration of boron into and through the gate oxides of p-channel MOSFETs that use p/sup +/ doped polysilicon gates. Boron penetration results in large positive shifts in V/sub FB/, increased p-channel subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Inclusion of a phosphorus coimplant or TiSi/sub 2/ salicide is shown to minimize this effect. The boron penetration phenomenon is modeled by the creation of a very shallow, fully depleted p-type layer in the silicon substrate close to the SiO/sub 2/-Si interface. Elemental boron is shown to be superior to BF/sub 2/ as an implant species for surface channel submicron PMOS devices.<<ETX>>

A high-performance 0.5- mu m BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5- mu m BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 mu m/sup 2/ by creating self-aligned bit-sense and V/sub ss/ contacts. A WSi/sub x/ polycide emitter n-p-n transistor with an emitter area of 0.8*2.4 mu m/sup 2/ provides a peak cutoff frequency (f/sub T/) of 14 GHz with a collector-emitter breakdown voltage (BV/sub CFO/) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f/sub T/ and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process. >

A high performance 0.5 mu m BiCMOS triple polysilicon technology for 4 Mb fast SRAMs

A high-performance 0.5 mu m BiCMOS technology has been developed which uses a triple polysilicon process architecture for a 4 Mb fast SRAM class of products. Three layers of polysilicon are used to achieve a compact four transistor cell size that is less than 20 mu m/sup 2/ by creating self-aligned bit-sense and Vss contacts to the four transistor cell. A WSi/sub x/ polycide emitter n-p-n transistor has been implemented with an emitter area of 0.8*2.4 mu m/sup 2/ and peak cutoff frequency (f/sub T/) of 14 GHz. A selectively ion implanted collector has been used to compensate the base channeling tail as well as to increase knee current and f/sub T/, while maintaining a collector to emitter breakdown voltage of 6.5 V. A minimum ECL gate delay of 115 ps has been achieved at a gate current of 400 mu A.<<ETX>>

A high-performance sub-half micron CMOS technology for fast SRAMs

An advanced high-performance sub-half-micron technology for fast CMOS SRAMs (static RAMs) has been developed. Features of this thin-well process include: an aggressive interwell isolation module, framed-mask poly-buffered LOCOS isolation (FMPBL), a 125-AA gate oxide, dual n/sup +//p/sup +/ implanted polysilicon gates, titanium salicide, two levels of polysilicon, TiN metallization barriers, a poly plug option, and up to three layers of metallization. An interwell isolation process allows scaling of the n/sup +/ to p/sup +/ space to less than 2 mu m. Active transistor design is optimized to reduce the polysilicon gate birds beak and LDD (lightly doped drain) underdiffusion. Discrete transistor lifetimes for hot carrier degradation are in excess of 10 years of 3.3-V operation. A 16 K*4 SRAM displays no parametric shifts after HCl stressing for 1000 h at 7 V and 0 degrees C. Ring oscillator delay times of 85 ps at 3.3-V and 65 ps at 5-V supply are obtained.<<ETX>>

A cobalt salicide CMOS process with TiN-strapped polysilicon gates

A submicrometer CMOS technology with MOSFET structures consisting of a TiN-strapped polysilicon gate electrode and self-aligned cobalt silicided source/drain junctions is developed. It is shown that the TiN-strapped gates provide a low-sheet-resistance gate electrode without threshold voltage instabilities caused by the lateral dopant interdiffusion of silicided gates. Cobalt silicide creep over the sidewall spacer, which can result in bridging between the source/drain and gate, is also eliminated. Since the source-drain regions are silicided with CoSi/sub 2/, shallow, low-leakage junctions are obtained.<<ETX>>

A high-performance half-micrometer generation CMOS technology for fast SRAMs

An advanced, high-performance, half-micrometer generation technology has been developed for fast CMOS SRAM circuits. This process features an aggressive interwell isolation module which allows scaling of the n/sup +/ to p/sup +/ space to less than 2 mu m and an advanced framed-mask poly-buffered LOCOS isolation (FMPBL) which reduces field oxide encroachment and the transistor narrow-width effect and provides a 1.2- mu m active pitch. Transistors are fabricated with a 125-A gate oxide and a dual n/sup +//p/sup +/ source/drain implanted polysilicon gates to provide excellent short-channel behavior down to 0.3- mu m effective channel length. Transistor design is optimized to reduce the polysilicon gate birds beak and lightly doped drain (LDD) underdiffusion. For PMOS transistors, boron diffusion through the gate oxide is minimized by replacing BF/sub 2/ with B/sup 11/ for the p/sup +/ S/D implant. A titanium salicide process provides strapping between n/sup +//p/sup +/ polysilicon gates and lower sheet and contact resistances. The back-end features three levels of metallization and polysilicon contact plugs. Discrete transistor lifetimes for DC hot-carrier degradation are in excess of 10 years at 3.3-V operation. A 16 K* 4 SRAM displayed no parametric shifts after hot-carrier stressing for 1000 h at 7-V and 0 degrees C. This is consistent with a lifetime of greater than 10 years at 3.3-V operation. Ring oscillator delay times of 85 ps at 3.3-V and 65 ps at 5-V supply are achieved. >

Kinetic analysis of silicon oxidations in the thin regime by incremental growth

The scaling of dry thermal oxides into the thin (<400 A) range continues to motivate studies of the rapid initial oxidation rate of silicon unaccounted for by a linear‐parabolic model. In this paper, silicon oxidation kinetics in this unresolved regime are studied by the incremental reoxidation of thin thermally grown and deposited silicon oxide layers on silicon. It is found that the reoxidation rates of thermally grown oxides in the thin regime rapidly decrease with increasing oxide thickness. In contrast, the reoxidation rates of deposited oxides are faster, and nearly thickness independent. It is also found that the reoxidation rates of thin thermal oxides can be significantly increased by inert thermal annealing. Existing thin‐regime oxidation models are evaluated in light of these experimental findings, and it is concluded that only models invoking stress suppression of early oxidation kinetics can reconcile all experimental observations. In further support of a stress argument, the time and tempera...

Use of screening and response surface experimental designs for development of a 0.5- mu m CMOS self-aligned titanium silicide process

A manufacturable self-aligned titanium silicide process for 0.5- mu m CMOS technologies has been developed. Factorial and fractional-factorial screening experiments, as well as physical models, were used to identify important process factors. Central-composite and D-optimal response surface designs were used to optimize the process; short-loop process and device experiments and 0.5- mu m technology static random access memory (SRAM) circuit flows were used. By using this comprehensive experimental design methodology, problems with diode leakage and silicide-to-silicon contact resistance were resolved, and specified device characteristics were achieved. >

A TiN strapped polysilicon gate cobalt salicide CMOS process

A novel TiN strapped polysilicon gate cobalt salicide process has been developed for a submicron CMOS technology. The resulting MOSFET structure consists of a TiN strapped polysilicon gate electrode and self-aligned cobalt silicided source/drain junctions. This structure provides a low-sheet-resistance polysilicon gate with shallow, low-leakage source/drain junctions, while avoiding the lateral dopant interdiffusion of silicided gates. Furthermore, the TiN strapped layer eliminates cobalt silicide creep and bridging over the oxide sidewall spacers between the gate and source/drain regions.<<ETX>>