Asanga H. Perera

NON-VOLATILE MEMORY (NVM) AND HIGH-K AND METAL GATE INTEGRATION USING GATE-LAST METHODOLOGY

Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates

Nonvolatile memory bitcell with inlaid high k metal select gate

Non-volatile memory (NVM) cell, high voltage transistor, and high-K and metal gate transistor integration

Method of Forming Different Voltage Devices with High-K Metal Gate

Integrated split gate non-volatile memory cell and logic device

Method of gate strapping in split-gate memory cell with inlaid gate

Integrated split gate non-volatile memory cell and logic structure

Methods and structures for charge storage isolation in split-gate memory arrays

SPLIT-GATE NON-VOLATILE MEMORY (NVM) CELL AND METHOD THEREFOR