Cristian Pavao Moreira
University of Bordeaux
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Featured researches published by Cristian Pavao Moreira.
ieee international newcas conference | 2006
Mustapha El Hassan; Cristian Pavao Moreira; Alexandre Shirakawa; Eric Kerherve; Yann Deval; Didier Belot; Andrea Cathelin
This article presents a dual-standard RF receiver front-end (RFFE). It consists of a reconfigurable FBAR filter using MEMS switches, a dual-standard low-noise amplifier (LNA), an active single-to-differential converter (SDC) and I/Q down conversion mixers. The proposed RFFE is targeted to W-LAN 802.11b/g (2.4-2.48 GHz) and W-CDMA-FDD (2.11-2.17 GHz) wireless standards. The active blocks use the 0.25-mum SiGe:C BiCMOS process from STMicroelectronics. The feasibility of BiCMOS compatible integrated tunable FBAR filter in BAW technology enables a very compact solution through module integration
european microwave conference | 2006
Cristian Pavao Moreira; Eric Kerherve; Pierre Jarry; Didier Belot
We present in this article a dual-standard dual-mode low-noise amplifier (LNA) for DCS1800/W-CDMA-FDD applications. In order to save die area compared to conventional parallel LNAs, we have used an alternative circuit configuration. It consists of sharing the most die consuming elements (inductances) in both operation standards, enabling a more compact solution. The mode and standard selection is performed through a bias scheme (MOS switches) that allows alternating between the two involved standards. The LNA die area is 1.0 times 1.2 mm2 and it consumes 6.8mW (3.8mA under 1.8V), including bias circuitry
european microwave conference | 2006
Cristian Pavao Moreira; E. Kerheve; Pierre Jarry; Didier Belot
This paper presents a dual-band concurrent fully-integrated low noise amplifier (LNA) targeted to W-LAN IEEE 802.11b/g/a standards. The use of a concurrent topology enables saving important die area and power consumption compared to the parallel solution that employs two separated LNAs. An original design methodology that helps selecting input/output matching network element values is also presented. The LNA die area is 1.0 times 0.9 mm2 and it consumes 9mW (5mA under 1.8V)
symposium on integrated circuits and systems design | 2005
Cristian Pavao Moreira; Alexandre Shirakawa; Eric Kerherve; Jean-Marie Pham; Pierre Jarry; Didier Belot; Pascal Ancey
This article presents guidelines to design a dual-standard fully-integrated RF receiver front-end (RFFE). The designed front-end consists of two system selection integrated FBAR filters, a dual-standard low-noise amplifier (LNA), an active single-to-differential converter (SDC) and I/Q downconversion mixers. The active blocks use the 0.25-mum 60-GHz fT SiGe:C BiCMOS7RF process from STMicroelectronics. The proposed RFFE is targeted to DCS1800 (1805-1880MHz) and W-CDMA-FDD (2110-2170MHz) wireless standards. The availability of integrated FBAR filters in BAW technology, compatible with the used BiCMOS process, enables a very compact solution through a module integration
bipolar/bicmos circuits and technology meeting | 2006
Cristian Pavao Moreira; Eric Kerherve; Pierre Jarry; Didier Belot
This paper presents a new BiFET concurrent fully-integrated low noise amplifier (LNA) targeted to W-CDMA/WLAN IEEE 802.11a standards. The use of a concurrent topology enables saving important die area and power consumption compared to the parallel solution that employs two separated LNAs. A design methodology that helps selecting input/output matching network element values is also presented
symposium on integrated circuits and systems design | 2005
Cristian Pavao Moreira; Eric Kerherve; Pierre Jarry; Didier Belot
We present in this article guidelines to design a dual-standard dual-mode low-noise amplifier (LNA) for DCS1800/W-CDMA applications. In order to save die area compared to conventional parallel LNAs, we have used an alternative circuit configuration. It consists of sharing the most die consuming elements (inductances) in both operation standards, enabling a more compact solution. The mode and standard selection is performed through a bias scheme (MOS switches) that allows alternating between the two involved standards. Good performances in terms of gain (S21 > 14.6dB), noise figure (NF ap 1.1dB) and input impedance matching (S11 < -26dB) were obtained. This was due mainly to the use of appropriated design and optimization techniques. The proposed dual-standard dual-mode LNA consumes 6.8mW under 1.8V supply voltage, in both standards
international conference on electronics, circuits, and systems | 2005
Cristian Pavao Moreira; Eric Kerherve; Pierre Jarry; Didier Belot
This paper presents guidelines to design a fully-integrated low-consumption BiFET low-noise amplifier targeted to WCDMA-FDD (2110-2170 MHz) system applications. It uses a high performance 0.25-mum SiGe:C BiCMOS7RF process from STMicroelectronics. The main motivation of this work is to evidence the advantages of a mixed Bipolar mosFET (BiFET) cascode topology, mainly in terms of linearity and power consumption. The LNA achieves a power gain of around 15.8 dB (250 MHz -1 dB bandwidth), a noise figure of 1.76 dB, an ICP1 and IIP3 of -9 dBm and 0 dBm, respectively. It consumes only 3.3 mW under 2.2 V supply voltage.
european microwave conference | 2005
Eric Kerherve; Cristian Pavao Moreira; Pierre Jarry; Laurent Courcelle
With the use GaAs pseudomorphic high electron-mobility transistor technology, the bandwidth performances of Cherry-Hooper driver amplifiers need to be improved. To fulfill these requirements, we propose an original driver circuit topology dedicated to 40-Gb/s optical communication systems. To flatten the transducer gain response of the circuit, passive networks have been added in the design. These networks have been optimized by means of the real frequency technique (RFT). A modified procedure of the classical RFT is introduced to perform the optimization in the presence of an overall resistive feedback.
2007 IEEE Northeast Workshop on Circuits and Systems | 2007
Cristian Pavao Moreira; Eric Kerherve; Pierre Jarry; Thierry Taris; Didier Belot
This paper presents a fully-integrated low-noise amplifier (LNA) to W-CDMA applications. A noise/input impedance matching methodology is applied to design the input stage of the LNA cascode topology. For circuit manufacturing, we have used a BiCMOS SiGe:C 0.25mum process which is well suited to low-noise applications. Good overall measured performances, in good agreement with simulation, are obtained.
international conference on electronics, circuits, and systems | 2006
Cristian Pavao Moreira; Eric Kerherve; Pierre Jarry; Didier Belot
We present is this article consistent guidelines to the design and implementation of fully-integrated BiFET low noise amplifiers (LNA). The effectiveness of BiFET topology and the applied methodologies are verified throughout measurement results of two fabricated BiFET LNAs. The first LNA is dedicated to W-CDMA applications (2.11-2.17 GHz) and its die area is 1.0 times 0.7 mm2. The second manufactured circuit is targeted to W-LAN IEEE 802.11a standard in European band (5.15-5.35 GHz). The W-LAN LNA die area is 1.0 times 0.57 mm2.