S.C. Kuehne

Spatial temperature profiles due to nonuniform self-heating in LDMOS's in thin SOI

Temperature profiles resulting from self-heating in SOI-LDMOS devices with uniformly doped and linearly graded drift regions were measured using a resistance thermometry technique. Two-dimensional electrothermal device simulations were performed and the results agreed with the experiments. Because of the different power dissipation profiles, RESURF devices with a uniformly doped drift region assume a fairly uniform temperature distribution while devices with a linearly graded drift region have a much higher temperature rise near the source than the drain. This local hot spot near the source raises reliability issues in device design.

High voltage LDMOS transistors in sub-micron SOI films

Silicon-on-insulator (SOI) LDMOS transistors with a linearly graded doping profile in the drift region have been found to exhibit both low on-resistance and high breakdown voltage. High-side operation is a problem for devices built in very thin SOI layers due to pinch-off of the drift region. This is less of a problem for devices built in thicker SOI layers. Devices built in thicker SOI films also are more tolerant of manufacturing variations and offer more predictable behaviour. Non-uniform self-heating within the drift region has been measured for the first time. A breakdown voltage of 1020 V is reported for a LDMOS transistor made in a 0.15 /spl mu/m SOI layer.

SOI MOSFET with buried body strap by wafer bonding

Although the buried oxide in the silicon-on-insulator (SOI) MOSFET makes possible higher performance circuits, it is also responsible for various floating body effects, including the kink effect, drain current transients, and history dependence of output characteristics. It is difficult to incorporate an effective contact to the body because of limitations imposed by the SOI structure. One candidate, which maintains device symmetry, is the lateral body contact. However, high lateral body resistance makes the contact effective only in narrow width devices. In this work, a buried lateral body contact in SOI is described which consists of a low-resistance polysilicon strap running under the MOSFET body along the device width. MOSFETs with effective channel length of 0.17 /spl mu/m have been fabricated incorporating this buried body strap, showing improved breakdown characteristics. Low leakage of the source and drain junctions demonstrates that the buried strap is compatible with deep submicron devices. Device modeling and analysis are used to quantify the effect of strap resistance on device performance. By accounting for the lateral resistance of the body, the model can be used to determine the maximum allowable device width, given the requirement of maintaining an adequate body contact.

Enhanced diffusion by electrical deactivation of arsenic and its implications for bipolar devices

In this paper, we present experiments designed to show enhanced diffusion of dopants due to the electrical deactivation of implanted arsenic or arsenic in-diffused from polysilicon. Results show a clear enhancement of diffusion in a nearby boron layer as well as an enhancement for the arsenic itself at an annealing temperature of 750/spl deg/C. At 500/spl deg/C, more typical of backend processing, no enhancement is detected in accordance with the very slow deactivation process at this temperature. Implications for bipolar devices were also investigated. Large differences in device characteristics were measured due to the enhanced diffusion. Secondary ion mass spectrometry (SIMS) analysis and simulation confirmed that enhanced diffusion of both arsenic and boron is the cause for the change in device characteristics. Evidence is also presented demonstrating that the order of the anneals is crucial, thereby rejecting the hypothesis of a full coupled diffusion effect as seen for phosphorus.

Evidence of reduced maximum E-field in quasi-SOI MOSFETs

A novel MOSFET device structure known as Quasi-SOI (QSOI MOSFET) permits direct measurements of substrate current generated by impact ionization near the SOI drain. It is observed that QSOI devices with identical dimensions and fabricated on the same wafer as bulk devices have lower substrate current when subjected to the same biases. We present here simulated and experimental evidence leading to the conclusion that the lateral maximum electric field near the drain is indeed lower in QSOI devices, with important implications for enhanced reliability in true SOI MOSFETs.

Application of selective epitaxial silicon and chemo-mechanical polishing to bipolar transistors

Successful demonstration of single-polysilicon bipolar transistors fabricated using selective epitaxial growth (SEG) and chemo-mechanical polishing (CMP) is reported. The pedestal structure made possible by the SEG/CMP process combination results in significantly reduced extrinsic-base collector capacitance. Cut-off frequency (f/sub T/) of devices with emitter stripe width of 1 /spl mu/m, a base width of 110 nm, and a peak base doping of 3/spl times/10/sup 18/ cm/sup -3/ have been observed to improve from 16 GHz to 22 GHz when the extrinsic-base collector overlap is decreased from 1 /spl mu/m to 0.2 /spl mu/m. Leakage current, often a problem for SEG structures, has been reduced to 27 nA/cm/sup 2/ for the area component, and 10 nA/cm for the edge component, by (1) appropriate post-polish processing, including a high-temperature anneal and sacrificial oxidation, (2) aligning the device sidewalls along the direction, and (3) the presence of the pedestal structure. Base-emitter junction nonideality in these transistors has also been investigated. >

Contact technology for high performance scalable BiCMOS on TFSOI

A selective W contact layer is deposited on both poly and silicon electrodes to realize scalable, high performance TFSOI BiCMOS. A unique double spacer integration results in high performance MOS and bipolar operation while providing adequate separation between poly and silicon electrodes to prevent sidewall leakage. Switching speed more than twice that of comparable bulk circuits is demonstrated. Limitations imposed by conventional silicon- and metal-diffusing self aligned silicides (Ti and Pt) are described. Pt silicide limits scaling of the spacer width while Ti silicide limits scaling of the silicon thickness. Selective W is shown capable of maintaining good device and circuit performance while not imposing such limitations.<<ETX>>

Device implications of enhanced diffusion caused by the electrical deactivation of arsenic

In this paper, we present experiments designed to show that electrical deactivation of arsenic enhances the diffusion of dopants for implanted arsenic or arsenic in-diffused from polysilicon. Results show a clear enhancement of diffusion in a nearby boron layer as well as an enhancement for the arsenic itself. Simulations and device measurements reveal this can have a considerable effect on the electrical characteristics of bipolar transistors.<<ETX>>

Single-poly bipolar transistor with selective epitaxial silicon and chemo-mechanical polishing

Fabrication of bipolar transistors employing selective epitaxial growth (SEG) and chemo-mechanical polishing (CMP) is demonstrated. The SEG/CMP combination allows for lithography-limited isolation and results in inherently planar surfaces. The pedestal structure made possible by these technologies facilitates reduction of extrinsic base-collector capacitance and reduces the edge leakage common in SEG structures. The pedestals protect the SEG sidewalls from any potential contaminants or oxidation-induced stress during subsequent processing, and hence help eliminate any induced leakage.<<ETX>>

A selective CVD tungsten-strapped polysilicon local interconnection technology

A local interconnection technology utilizing polysilicon strapped with selective-chemical-vapor-deposited (CVD) tungsten has been developed. Both n- and p-channel MOS transistors have been successfully fabricated using this technology. Tungsten deposited on polysilicon is an attractive gate shunt and local interconnection material because of its low resistivity, immunity to dopant segregation and diffusion, and resistance to electromigration. A potential problem of this technology is the excessive diode leakage current associated with strapping shallow source/drain diodes with tungsten. The leakage is attributed to defects induced by the heavy source/drain implant, which can be effectively eliminated with a proper annealing procedure. >