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Dive into the research topics where Ying-Keung Leung is active.

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Featured researches published by Ying-Keung Leung.


symposium on vlsi technology | 2015

In 0.53 Ga 0.47 As MOSFETs with high channel mobility and gate stack quality fabricated on 300 mm Si substrate

Mao-Lin Huang; S. W. Chang; Meng-Ku Chen; C. H. Fan; Hau-Yu Lin; Chun-Hsiung Lin; R. L. Chu; K. Y. Lee; M. A. Khaderbad; Z. C. Chen; Chao-Cheng Chen; L. T. Lin; Hung-Ta Lin; Hui-Cheng Chang; Chang-Ta Yang; Ying-Keung Leung; Yee-Chia Yeo; Syun-Ming Jang; H. Y. Hwang; Carlos H. Diaz

In<sub>0.53</sub>Ga<sub>0.47</sub>As channel MOSFETs were fabricated on 300 mm Si substrate. The epitaxial In<sub>0.53</sub>Ga<sub>0.47</sub>As channel layer exhibits high Hall electron mobility comparable to those grown on lattice matched InP substrates. Excellent device characteristics (SS~95 mV/dec., I<sub>on</sub>/I<sub>off</sub> ~10<sup>5</sup>, DIBL ~51 mV/V at V<sub>ds</sub> = 0.5V for L<sub>g</sub>=150 nm device) with good uniformity across the wafer were demonstrated. The extracted high field effect mobility (μ<sub>EF</sub> = 1837 cm<sup>2</sup>/V-s with EOT ~ 0.9 nm) is among the highest values reported for surface channel In<sub>0.53</sub>Ga<sub>0.47</sub>As MOSFETs.


custom integrated circuits conference | 2005

Device trends and implications on circuit design in advanced CMOS technologies

Carlos H. Diaz; K. H. Fung; Ying-Keung Leung; Chung-Cheng Wu; Chih-Ping Chao; G. J. Chern; Wesley Lin; Chia-Fu Lee; Fang-Shi Lai; Mi-Chang Chang; Yuan-Chen Sun

To conciliate scaling-driven fundamental material limitations with industry evolution requirements, flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize systems on a chip (SoC). This paper discusses issues associated with power supply scaling, performance-leakage power optimization including dynamic body/well bias, gate dielectric scaling, mobility enhancement by strained-Si, SRAM process and design interactions, digital and analog device tradeoffs, and HV I/O considerations in advanced CMOS technologies.


Archive | 2003

Recessed gate structure with reduced current leakage and overlap capacitance

Da-Wen Lin; Yi-Ming Sheu; Ying-Keung Leung


Archive | 2016

DEVICES INCLUDING GATE SPACER WITH GAP OR VOID AND METHODS OF FORMING THE SAME

Kuo-Cheng Ching; Ching-Wei Tsai; Chi-Wen Liu; Ying-Keung Leung


Archive | 2017

MULTI-GATE DEVICE AND METHOD OF FABRICATION THEREOF

Kuo-Cheng Ching; Chung-Cheng Wu; Ching-Fang Huang; Wen-Hsing Hsieh; Ying-Keung Leung; Cheng-Ting Chung


Archive | 2017

FINFET WITH SOURCE/DRAIN STRUCTURE AND METHOD OF FABRICATION THEREOF

Kuo-Cheng Ching; Ching-Wei Tsai; Ying-Keung Leung


Archive | 2016

Stacked Gate-All-Around FinFET and Method Forming the Same

Kuo-Cheng Ching; Chi-Wen Liu; Ying-Keung Leung


Archive | 2015

Contacts For Highly Scaled Transistors

Carlos H. Diaz; Chung-Cheng Wu; Chia-Hao Chang; Chih-Hao Wang; Jean-Pierre Colinge; Chun-Hsiung Lin; Wai-Yi Lien; Ying-Keung Leung


Archive | 2017

METHOD OF TUNING SOURCE/DRAIN PROXIMITY FOR INPUT/OUTPUT DEVICE RELIABILITY ENHANCEMENT

Kuo-Cheng Ching; Ching-Wei Tsai; Chih-Hao Wang; Ying-Keung Leung


Archive | 2017

FINFETS with Wrap-Around Silicide and Method Forming the Same

Kuo-Cheng Ching; Ching-Wei Tsai; Chi-Wen Liu; Chih-Hao Wang; Ying-Keung Leung

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