Cynthia D. Baringer

A silicon bipolar broadband PLL building block integrated circuit

A broadband phase-lock loop building block IC that can accommodate signal frequencies from 0.5 GHz to 9 GHz is presented. The design integrates a prescaler with selectable divide ratio, a phase detector, a voltage-controlled oscillator for production testing, and associated circuitry. The chip is designed in a silicon bipolar linear array technology and packaged in a 16-pin plastic dual in-line package. The result is a low-cost, broadband solution for a variety of PLL systems.

A clock phase adjustment circuit for synchronizing multiple high-speed DEMUXs

A 2:16 DEMUX IC with clock phase adjustment has been successfully designed, fabricated, and tested as an interfacing component in 30 Gbps and higher transmission systems using HRLs 0.25 μm low power InP DHBT technology with ft of 400 GHz. The novel clock phase adjustment circuit described here allows multiple DEMUXs to be automatically synchronized eliminating the need of complex clock recovery circuits. The IC uses 1460 DHBTs and consumes only 1.85 W of power demonstrating the feasibility of InP DHBTs in low power and large integration ICs.

Mixed-Signal Circuits Using 250nm InP HBT Technology Integrated with 90nm CMOS

Digital Analog converters using InP HBTs and 90nm CMOS have been designed using the novel HRL integration process developed under the DARPA COSMOS program. These circuits demonstrate that this process is capable of providing a compelling alternative to traditional Si/SiGe BiCMOS implementations for producing highly integrated state-of-the-art mixed signal and digitally-assisted analog circuits.