Yen-Cheng Kuan

An adaptive RTS/CTS control mechanism for IEEE 802.11 MAC protocol

We study the impact of using or disengaging the RTS/CTS dialogue in IEEE 802.11 DCF MAC protocol under the fact that carrier sensing, transmission and interference ranges are distinctively different. The resulting throughput performance features of a linear topology network configuration are demonstrated when applying constant bit rate (CBR) UDP as well as TCP type traffic flows. Based on these results, we propose a new RTS/CTS control mechanism. Under our scheme, a terminal node decides dynamically and individually whether to use a RTS/CTS dialogue for the transmission of its current data packet. We show that this new mechanism yields distinctive performance improvements.

A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications

A 7-bit, 2.2-GS/s time-interleaved subranging CMOS analog-to-digital converter (ADC) for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling distributed resistor array for reference voltages is proposed to mitigate gain mismatches within channels. Moreover, the channel offset mismatches are calibrated through the digital- controlled corrective current sources embedded in the track-and-hold amplifiers of each sub-ADC. The prototype is implemented in 65 nm CMOS, occupying only 0.3 mm2 chip area and consuming 40 mW at 2.2 GS/s from a 1 V supply. Measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 38 dB and 46 dB, respectively, with a 1.08 GHz input at 2.2 GS/s sampling rate. The effective number of bits (ENOB) is 6.0 bits at Nyquist rate, and the figure-of-merit (F.O.M.) is 0.28 pJ/conv.-step. This prototype has also been integrated into a gigabit self-healing wireless transceiver SoC.

14.9 Sub-sampling all-digital fractional-N frequency synthesizer with −111dBc/Hz in-band phase noise and an FOM of −242dB

The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal [1-2]. This results in coarser TDC resolution and worse ADPLL noise performance. This paper presents a fractional-/VADPLL that employs a new time-to-digital conversion technique based on sub-sampling phase detection. It is accomplished by directly sampling the analog voltage signal at the PLLs high frequency node and converting it into a digital code. This achieves a higher time resolution with less power.

A low-overhead self-healing embedded system for ensuring high yield and long-term sustainability of 60GHz 4Gb/s radio-on-a-chip

The available ISM band from 57-65GHz has become attractive for high-speed wireless applications including mass data transfer, streaming high-definition video and even biomedical applications. While silicon based data transceivers at mm-wave frequencies have become increasingly mature in recent years [1,2,3], the primary focus of the circuit community remains on the design of mm-wave front-ends to achieve higher data rates through higher-order modulation and beamforming techniques. However, the sustainability of such mm-wave systems when integrated in a SoC has not been addressed in the context of die performance yield and device aging. This problem is especially challenging for the implementation of mm-wave SoCs in deep sub-micron technology due to its process & operating temperature variations and limited ft / fmax with respect to the operation frequency.

A 65nm CMOS 140 GHz 27.3 dBm EIRP transmit array with membrane antenna for highly scalable multi-chip phase arrays

This paper presents a scalable transmit phase array operating at 140 GHz which employs a local PLL reference generation system. Unlike traditional CMOS phase arrays, this enables the array to be formed over multiple chips while avoiding the challenges of distributing mm-wave signals between them. The prototype chip consumes 131 mW of power and occupies 1.95 mm2 of chip area when implemented in 65 nm CMOS technology.

A Current-Mode mm-Wave direct-conversion receiver with 7.5GHz Bandwidth, 3.8dB minimum noise-figure and +1dBm P 1dB, out linearity for high data rate communications

A current-mode mm-wave direct-conversion receiver breaking trade-offs among bandwidth, NF and linearity is designed and realized in 65nm CMOS. The 60GHz receiver employs novel Frequency-staggered Series Resonance Common Source (FSRCS) stage to extend RF bandwidth with superior noise performance. The receivers current-mode operation offers excellent out-of-band blocker tolerance and linearity. With on-chip quadrature LO generations, the fabricated receiver simultaneously achieves minimal noise figure of 3.8dB, RF bandwidth of 7.5GHz, output P1dB of 1dBm, maximum conversion gain of 32dB, and IRR of -35dB. The receiver is capable of tolerating outof-channel blocker up to -9dBm at 3.5GHz away. It occupies silicon area of 1.3mm2 and draws 25.5mA from 1V supply.

Wireless Gigabit Data Telemetry for Large-Scale Neural Recording

Implantable wireless neural recording from a large ensemble of simultaneously acting neurons is a critical component to thoroughly investigate neural interactions and brain dynamics from freely moving animals. Recent researches have shown the feasibility of simultaneously recording from hundreds of neurons and suggested that the ability of recording a larger number of neurons results in better signal quality. This massive recording inevitably demands a large amount of data transfer. For example, recording 2000 neurons while keeping the signal fidelity (> 12 bit,> 40 KS/s per neuron) needs approximately a 1-Gb/s data link. Designing a wireless data telemetry system to support such (or higher) data rate while aiming to lower the power consumption of an implantable device imposes a grand challenge on neuroscience community. In this paper, we present a wireless gigabit data telemetry for future large-scale neural recording interface. This telemetry comprises of a pair of low-power gigabit transmitter and receiver operating at 60 GHz, and establishes a short-distance wireless link to transfer the massive amount of neural signals outward from the implanted device. The transmission distance of the received neural signal can be further extended by an externally rendezvous wireless transceiver, which is less power/heat-constraint since it is not at the immediate proximity of the cortex and its radiated signal is not seriously attenuated by the lossy tissue. The gigabit data link has been demonstrated to achieve a high data rate of 6 Gb/s with a bit-error-rate of 10-12 at a transmission distance of 6 mm, an applicable separation between transmitter and receiver. This high data rate is able to support thousands of recording channels while ensuring a low energy cost per bit of 2.08 pJ/b.

A 95 GHz centimeter scale precision confined pathway system-on-chip navigation processor for autonomous vehicles in 65nm CMOS

This paper presents a 95 GHz centimeter scale navigation system which allows a unmanned ground vehicle (UGV) or possibly even aerial vehicle (UAV) to navigate through a highly cluttered environment and follow a safe obstacle-free pathway to a desired goal. The navigation system defines multiple pathways using mm-wave base-stations called path generators and then uses a single CMOS SoC containing a receiver, ADC and an FFT processor to detect and navigate these pathways. The demonstrated confined pathway SoC (CP-SoC) occupies 5.4mm2 of silicon area in 65nm technology, and consumes only 199 mW, making it suitable for lightweight payloads associated with UAVs and UGVs.

A 200 GHz 16-pixel focal plane array imager using CMOS super regenerative receivers with quench synchronization

We have realized a 200GHz 4×4 focal plane array (FPA) by using super-regenerative receiver (SRR) pixels made of 65nm CMOS for mm-wave imaging applications. With 16 pixel elements constructed on PCB, the FPA consumes 215mA under 1V power supply. Such realization is made possible by carefully analyzing the super-regenerative interference (SRI) commonly observed in close-spaced SRRs and applying a newly developed quench synchronization scheme to suppress the undesired SRI.

A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS

A 7-bit, 2.2-GS/s time-interleaved subranging CMOS ADC for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A novel time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling distributed resistor array for reference voltages is proposed to mitigate mismatches within channels. The prototype is implemented in 65 nm CMOS, occupying only 0.3 mm2 chip area and consumes 40 mW at 2.2 GS/s from a 1 V supply. Measured SNDR and SFDR are 38 dB and 46 dB, respectively, with a 1.08 GHz input at 2.2 GS/s sampling rate.