D. Donaghy

Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation

Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple self-aligned process has been developed to reduce the parasitic overlap capacitance in vertical MOSFETs using nitride spacers on the sidewalls of the trench or pillar and a local oxidation. This will result in an oxide layer on all exposed planar surfaces, but no oxide layer on the protected vertical channel area of the pillar. The encroachment of the oxide on the side of the pillar is studied by transmission electron microscopy (TEM) which is used to calibrate the nitride viscosity in the process simulations. Surround gate vertical transistors incorporating the spacer oxidation have been fabricated, and these transistors show the integrity of the process and excellent subthreshold slope and drive current. The reduction in intrinsic capacitance is calculated to be a factor of three. Pillar capacitors with a more advanced process have been fabricated and the total measured capacitance is reduced by a factor of five compared with structures without the spacer oxidation. Device simulations confirm the measured reduction in capacitance.

Design of 50-nm vertical MOSFET incorporating a dielectric pocket

A new architecture for a vertical MOS transistor is proposed that incorporates a so-called dielectric pocket (DP) for suppression of short-channel effects and bulk punch-through. We outline the advantages that the DP brings and propose a basic fabrication process to realize the device. The design issues of a 50-nm channel device are addressed by numerical simulation. The gate delay of an associated CMOS inverter is assessed in the context of the International Technology Roadmap for Semiconductors and the vertical transistor is seen to offer considerable advantages down to the 100-nm node and beyond due to the dual channels and the ability to produce a 50-nm channel length with more relaxed lithography.

Investigating 50nm Channel Length Vertical MOSFET Containing a Dielectric Pocket, in a Circuit Environment

The performance potential of a 50nm channel length vertical MOSFET (vMOS) architecture is assessed by numerical simulation and the use of a circuit level model. The vMOS architecture incorporates some novel features, namely a dielectric pocket for suppression of short channel effects and strategies to reduce parasitic overlap capacitance. The model allows quantification of performance limitations arising from drain and source overlap capacitances, which are shown to constitute up to 60% of the total inverter capacitance. The model allows some optimisation of performance from a circuit perspective. Comparison between a production lateral device and the vMOS device is made at the 350nm node although a 50nm channel can be realised at this node for the vMOS. The comparison is made for power supply, VDD ~ 4Vth. The dual channels and the reduced gate length aid the optimised 50nm vertical structure to operate 70% times faster at VDD=1V than the 350nm lateral device at VDD = 3V for a fan-out, N=10. For a loaded inverter, the performance advantages increases to a factor of 3.5. The model further predicts that the vertical 50nm inverter at VDD = 1V has an energy-delay product an order of magnitude lower than the 350nm lateral inverter at VDD=3V for a fan-out of 10.

Electrical characteristics of single, double & surround gate vertical MOSFETs with reduced overlap capacitance

The vertical MOSFET structure is one of the solutions for reducing the channel length of devices under 50 nm. Surround gate structures can be realized which offer improved short channel effects and more channel width per unit silicon area. In this paper, a low overlap capacitance, surround gate, vertical MOSFET technology is presented, which uses fillet local oxidation (FILOX) to reduce the overlap capacitance between the gate and the drain on the bottom of the pillar. Electrical characteristics of surround gate n-MOSFETs are presented and compared with results from single gate and double gate devices on the same wafer. The devices show good symmetry between the source on top and source on bottom configuration. The short channel effects of the surround gate MOSFETs are investigated.

Linker-free covalent immobilization of nisin using atmospheric pressure plasma induced grafting

The linker-free covalent immobilization of polymers on surfaces has the potential to impart new properties and functions to surfaces for a wide range of applications. However, most current methods for the production of these surfaces involve multiple chemical steps and do not have a high degree of control over the chemical functionalities at the surface. A comprehensive study detailing the facile two-step covalent grafting of the antimicrobial peptide nisin onto polystyrene surfaces is reported. Functionalization is achieved using an atmospheric pressure plasma jet, and the reaction is monitored and compared with a standard wet chemical functionalization approach using a variety of analytical techniques. The reactive species produced by the atmospheric pressure plasma jet were analyzed by mass spectrometry and optical emission spectroscopy. The surface chemistry and topography of the functionalized surfaces were determined using contact angle measurements, Fourier infrared spectroscopy (FTIR), X-ray photoelectron spectroscopy and atomic force microscopy respectively. Following surface analysis, the antimicrobial efficacy of the covalently grafted nisin against two major food borne pathogens (Staphylococcus aureus and Listeria monocytogenes) was assessed at two different pHs. The results demonstrated that a post-plasma treatment step after nisin deposition is required to covalently graft the peptide onto the surface. The covalent immobilization of nisin resulted in a significant reduction in bacterial counts within a short 30 minutes contact time. These surfaces were also significantly more antimicrobial compared to those prepared via a more traditional wet chemical approach indicating that the reported method could be a less expensive and less time consuming alternative.

Impact of universal mobility law on polycrystalline organic thin-film transistors

We have developed novel analytical models for polycrystalline organic thin-film transistor (OTFT) by employing new concepts on the charge carrier injection to polysilicon thin-films. The models, also incorporate the effect of contact resistance associated with the poor ohmic nature of the contacts. The drain current equations of the OTFT, both in the quasi-diffusion and quasi-drift regimes, predict temperature dependencies on essential material and device parameters. Interestingly, under the drift regime, the polycrystalline OTFT model reveals similar power dependencies on the applied voltages, to those of purely disordered model developed by utilizing the universal mobility law (UML). Such similarities are not thought to be coincidental since the effect of gate voltage on surface potential is influenced by the Fermi level pinning in the grain boundary. Nonetheless, the best fits on the data of 6,13-bis(tri-isopropylsilylethynyl) OTFTs are attained with the proposed polycrystalline rather than the disorde...

Design and simulation of a high-gain organic operational amplifier for use in quantification of cholesterol in low-cost point-of-care devices

This paper presents circuit design and simulations of a high gain organic Op-Amp, for use in quantification of real cholesterol, in the range of 1-9 mM. A 7-stage inverter chain is added onto the design so as to enhance the amplifier gain. The circuit adapts p-channel transistors only (PMOS) design architecture with saturated loads, simulated on a conventional platform, using appropriate OTFT model and associated parameters. The effect of variation in threshold voltage on circuit operation is also examined. For a supply voltage of ±15 V, the DC output voltage is found to be within an acceptable range of -1 V to -12.5 V, with a highest open loop gain of 83 dB. The closed loop gain is also in agreement with theoretical values, in the range of 1.5 dB to 39 dB, with corresponding bandwidths of 770 Hz to 275 Hz respectively. The latter gain of 39 dB and/or gain-bandwidth product of 10.63 kHz is currently the highest reported in the literature, for this lower supply voltage. The amplifier offers adequate quantification factor, with linear sensitivity of -0.7 V/mM. This paper is the first to adapt organic circuit designs in quantification of cholesterol, with promising outputs, for implementation in low-cost sensor systems.

Design of a high gain organic comparator for use in low-cost smart sensor systems

This paper presents novel designs of a 3-stage organic comparator, a key building block of an organic analogue-to-digital converter (ADC), for integration in low-cost smart sensor systems. The designs adopt a pseudo-PMOS configuration so as to allow ease of fabrication of the comparator. DC and transient analysis are carried out using modified silicon models with organic parameters, so as to accommodate the properties of an organic transistor. Two topologies of the comparator designs are simulated, with the aim of enhancing the overall gain. The effect of threshold voltage variation on the outputs of the two designs is also examined. For a variation of 1 V, small shifts in the output voltage of 0.01 V to 0.3 V are observed respectively. Moreover, the DC open loop gain for the two designs are found to range between 45.72 dB to 60.95 dB and 22.97 dB to 54.73 dB for the 1st and 2nd designs respectively. The latter gains of both designs are currently the highest reported in the literature for an organic comparator. In addition, the propagation delay and resolution also varied depending on the design, such that values of 0.05 ms to 0.16 ms and 0.3 V to 0.6 V were attained for the 1st design respectively, and 0.12 ms to 0.18 ms and 0.08 V to 0.8 V were attained for the 2nd design. Overall comparison of the two designs revealed that additional gain stages results in larger bandwidth and better resolution however it also reduces the output voltage swings, gain and operational speed. For use in sensor applications, particularly artificial skins and e-textile clothing, the output specifications of the 1st design are considered adequate, despite the trade-offs on the bandwidth and resolution.

Impact of the Universal Mobility Law on Polycrystalline Organic Device and Circuit Operation

We have developed an analytical model for polycrystalline-based organic thin-film transistors (OTFTs) that employs, as far as possible, new concepts on carrier injection to the conventional polysilicon model. The drain current equations, both in diffusion and drift regimes, predict the voltage and temperature dependencies on the various device and circuit parameters. Interestingly, upon direct comparison with previously developed disordered model, similarities between the two are not thought to be coincidental. The effect of gate voltage on surface potential is affected by the Fermi level pinning in the grain boundary, which is assumed to consist of mainly disordered material. This work also highlights the problem of using drift mobility, as an organic circuit design parameter, and consequently alternative quantities are proposed for simpler circuits such as an inverter. Upon validation of the model, relatively good fits are obtained with the experimental data on TIPS-based TFTs. The divergence at low drain voltages are thought to be associated with short channel and/or high contact resistance effects.

Variable Temperature Capacitance-Voltage Measurements to Investigate the Density of Localized Trapping Levels in Organic Semiconductors

We have approximated the tail of the Gaussian distribution of states of organic semiconduc-tors with an exponential function. We have used this approach to calculate the carrier concentra-tion in organic materials, and subsequently the charge distribution in the accumulation region of a field effect device and the space-charge capacitance in accumulation mode. Small signal high frequency capacitance-voltage measurements performed at various temperatures show good agreement with this model and the characteristic temperature of the exponential function has been estimated from these measurements based on the theory developed.